diff options
| author | Claire Wolf <clifford@clifford.at> | 2020-03-03 08:38:32 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-03 08:38:32 -0800 |
| commit | b597f85b13b5369398350ef4ef43b7b2521eb140 (patch) | |
| tree | 18ea3d52b5927ea1491162458e16cfcfd3280418 /kernel | |
| parent | 91892465e1af2bcb5ec348b86ba4e566b040cb12 (diff) | |
| parent | f80fe8dc22ca2b3639b7b0bbff69458addb05432 (diff) | |
| download | yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.tar.gz yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.tar.bz2 yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.zip | |
Merge pull request #1718 from boqwxp/precise_locations
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5d7e61901..06181b763 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3924,8 +3924,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri cover("kernel.rtlil.sigspec.parse"); AST::current_filename = "input"; - AST::use_internal_line_num(); - AST::set_line_num(0); std::vector<std::string> tokens; sigspec_parse_split(tokens, str, ','); |