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| author | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-02-23 07:19:52 +0000 |
|---|---|---|
| committer | Alberto Gonzalez <boqwxp@airmail.cc> | 2020-02-23 07:22:26 +0000 |
| commit | f0afd65035fefebdea8edbd00c916c5f33e8a634 (patch) | |
| tree | 5d34c5920dc230388c41bb7380e1241dec274fcf /kernel | |
| parent | 6edca05793197a846bbfb0329e836c87fa5aabb6 (diff) | |
| download | yosys-f0afd65035fefebdea8edbd00c916c5f33e8a634.tar.gz yosys-f0afd65035fefebdea8edbd00c916c5f33e8a634.tar.bz2 yosys-f0afd65035fefebdea8edbd00c916c5f33e8a634.zip | |
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 5d7e61901..06181b763 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3924,8 +3924,6 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri cover("kernel.rtlil.sigspec.parse"); AST::current_filename = "input"; - AST::use_internal_line_num(); - AST::set_line_num(0); std::vector<std::string> tokens; sigspec_parse_split(tokens, str, ','); |