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authorEddie Hung <eddie@fpgeh.com>2020-03-17 10:22:16 -0700
committerEddie Hung <eddie@fpgeh.com>2020-03-17 10:22:16 -0700
commitbc51e609cbe00948cf0cae4d58ff36616ff85679 (patch)
tree576fcfee9d962fffd7951b8a83b84faa0e20cdce /kernel
parent432a09af80f7dcba9fd517a001e3a1954c99537e (diff)
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kernel: fix DeleteWireWorker
Diffstat (limited to 'kernel')
-rw-r--r--kernel/rtlil.cc13
1 files changed, 4 insertions, 9 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 102b30241..79eb2a762 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1586,6 +1586,7 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
const pool<RTLIL::Wire*> *wires_p;
void operator()(RTLIL::SigSpec &sig) {
+ sig.pack();
for (auto &c : sig.chunks_)
if (c.wire != NULL && wires_p->count(c.wire)) {
c.wire = module->addWire(NEW_ID, c.width);
@@ -1599,16 +1600,10 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
rhs.unpack();
for (int i = 0; i < GetSize(lhs); i++) {
RTLIL::SigBit &lhs_bit = lhs.bits_[i];
- if (lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) {
- lhs_bit.wire = module->addWire(NEW_ID);
- lhs_bit.offset = 0;
- continue;
- }
RTLIL::SigBit &rhs_bit = rhs.bits_[i];
- if (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire)) {
- rhs_bit.wire = module->addWire(NEW_ID);
- rhs_bit.offset = 0;
- continue;
+ if ((lhs_bit.wire != nullptr && wires_p->count(lhs_bit.wire)) || (rhs_bit.wire != nullptr && wires_p->count(rhs_bit.wire))) {
+ lhs_bit = State::Sx;
+ rhs_bit = State::Sx;
}
}
}