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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 12:01:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | a6fec9fe6052d2ec74fec4417be2fec45dea0df0 (patch) | |
| tree | 92c3dda81a0d5946ce1f316da7a46afe1a871aa1 /kernel | |
| parent | 3ea5506f812879c0ecf66431efde002493e11bdf (diff) | |
| download | yosys-a6fec9fe6052d2ec74fec4417be2fec45dea0df0.tar.gz yosys-a6fec9fe6052d2ec74fec4417be2fec45dea0df0.tar.bz2 yosys-a6fec9fe6052d2ec74fec4417be2fec45dea0df0.zip | |
abc9_ops: use TimingInfo for -prep_{lut,box} too
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/timinginfo.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index f31fbaab4..b1a1b85ac 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -56,7 +56,7 @@ struct TimingInfo } } - void setup_module(RTLIL::Module *module) + const ModuleTiming& setup_module(RTLIL::Module *module) { auto r = data.insert(module->name); log_assert(r.second); @@ -146,10 +146,13 @@ struct TimingInfo } } } + + return t; } decltype(data)::const_iterator find (RTLIL::IdString module_name) const { return data.find(module_name); } decltype(data)::const_iterator end () const { return data.end(); } + int count (RTLIL::IdString module_name) const { return data.count(module_name); } }; YOSYS_NAMESPACE_END |