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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-01 14:17:45 -0700 |
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committer | GitHub <noreply@github.com> | 2020-04-01 14:17:45 -0700 |
commit | c90324662ce23e3444d6a7450153d8a4c3946b9a (patch) | |
tree | f4548e2c37f0257ac8d782909f1b0b68431a672d /kernel | |
parent | 4ae7f3a8edded54c33a92b02659167c8a6af2522 (diff) | |
parent | 1d93d1e59f5ce222886b785f0a0a553ceeb39c1c (diff) | |
download | yosys-c90324662ce23e3444d6a7450153d8a4c3946b9a.tar.gz yosys-c90324662ce23e3444d6a7450153d8a4c3946b9a.tar.bz2 yosys-c90324662ce23e3444d6a7450153d8a4c3946b9a.zip |
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
kernel: share a single CellTypes within a pass
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/modtools.h | 13 |
1 files changed, 3 insertions, 10 deletions
diff --git a/kernel/modtools.h b/kernel/modtools.h index 409562eb9..383b37589 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -380,22 +380,15 @@ struct ModWalker } } - ModWalker() : design(NULL), module(NULL) + ModWalker(RTLIL::Design *design) : design(design), module(NULL) { + ct.setup(design); } - ModWalker(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) + void setup(RTLIL::Module *module, CellTypes *filter_ct = NULL) { - setup(design, module, filter_ct); - } - - void setup(RTLIL::Design *design, RTLIL::Module *module, CellTypes *filter_ct = NULL) - { - this->design = design; this->module = module; - ct.clear(); - ct.setup(design); sigmap.set(module); signal_drivers.clear(); |