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* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-272-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* Update CopyrightClaire Wolf2020-03-161-1/+1
| | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* License: bump year and add titleWaldir Pimenta2020-03-141-1/+1
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* exclude clang from checkingMiodrag Milanovic2020-03-131-1/+1
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* Add YS_ prefix to macros, add explanation and apply to older version as wellMiodrag Milanovic2020-03-133-20/+23
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* Use boost xpressive for gcc 4.8Miodrag Milanovic2020-03-133-23/+29
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* Fix compilation for emccjiegec2020-03-112-1/+4
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* Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-092-0/+13
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+0
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-2/+0
| | | | | | | | and RTLIL nodes.
* | Small fixesEddie Hung2020-02-271-2/+2
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* | Fixes for older compilersEddie Hung2020-02-271-1/+8
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* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-4/+5
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* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-9/+19
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* | Fix spacingEddie Hung2020-02-271-50/+50
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* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-3/+4
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* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-1/+4
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* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-18/+2
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* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-0/+173
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* | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-263-2/+100
|\ \ | |/ |/| Logger pass
| * Remove duplicate warning detectionMiodrag Milanovic2020-02-231-0/+6
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| * Handle expect no warnings together with expectedMiodrag Milanovic2020-02-223-4/+12
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| * Prevent double error messageMiodrag Milanovic2020-02-171-1/+3
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| * Option to expect no warningsMiodrag Milanovic2020-02-173-0/+5
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| * No new error if already failingMiodrag Milanovic2020-02-171-1/+2
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| * remove whitespaceMiodrag Milanovic2020-02-141-1/+1
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| * Add expect option to logger commandMiodrag Milanovic2020-02-143-2/+78
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* | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+6
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* Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-295-3/+55
|\ | | | | Add log_experimental() and experimental() API and "yosys -x"
| * Improve logging use of experimental featuresClaire Wolf2020-01-283-4/+8
| | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
| * Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-275-3/+51
| | | | | | | | Signed-off-by: Claire Wolf <clifford@clifford.at>
* | Add and use SigSpec::reverse()Eddie Hung2020-01-281-0/+2
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* Merge pull request #1613 from porglezomp-misc/version-flag-aliasClaire Wolf2020-01-271-0/+6
|\ | | | | Add --version and -version as aliases for -V
| * Add --version and -version as aliases for -VCassie Jones2020-01-051-0/+6
| | | | | | | | | | | | | | | | The flag --version is commonly accepted by command line tools. The code for the version flags added here matches the pattern used for the help flag aliases, for consistency. Fixes #1612
* | As before, only display MEM if Linux or FreeBSDEddie Hung2020-01-141-3/+7
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* | print_stats footer to return peak memory, option for including childrenEddie Hung2020-01-141-28/+12
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* | Move abc9.* constpad entries to Abc9Pass::on_register()Eddie Hung2020-01-091-35/+0
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* | Merge remote-tracking branch 'origin/clifford/onpassreg' into ↵Eddie Hung2020-01-093-1/+20
|\ \ | | | | | | | | | eddie/abc9_scratchpad
| * | Add Pass::on_register() and Pass::on_shutdown()Clifford Wolf2020-01-093-1/+20
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add abc9.if.script.flow{,2} to constpadEddie Hung2020-01-081-6/+32
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* | Add RTLIL::constpad, init by yosys_setup(); use for abc9Eddie Hung2020-01-083-0/+12
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* Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputsClifford Wolf2020-01-021-4/+25
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-3/+21
| | | | | | | Before this commit, these cells would accept any \B_SIGNED and in case of \B_SIGNED=1, would still treat the \B input as unsigned. Also fix the Verilog frontend to never emit such constructs.
* Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
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* Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
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* log_dump() to support State enumEddie Hung2019-10-023-0/+6
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* Fix typoEddie Hung2019-09-301-1/+1
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* Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-302-3/+3
|\ | | | | Open aig frontend as binary file
| * Open aig frontend as binary fileMiodrag Milanovic2019-09-292-3/+3
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* | Merge pull request #1414 from hzeller/improve-replace-with-empty-mapEddie Hung2019-09-291-0/+2
|\ \ | |/ |/| Avoid work in replace() if rules empty.
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