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* Remove a statement without effect.Henner Zeller2023-04-171-2/+0
| | | | | | | The return value of the min(...) call is never used. Looks like some leftover from some previous implementation. Signed-off-by: Henner Zeller <h.zeller@acm.org>
* backends/rtlil: Do not shorten a value with z bits to 'xJannis Harder2023-01-292-0/+12
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* Merge pull request #3624 from jix/sim_ywMiodrag Milanović2023-01-235-0/+668
|\ | | | | Changes to support SBY trace generation with the sim command
| * sim/formalff: Clock handling for yw cosimJannis Harder2023-01-111-2/+2
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| * sim: Improvements and fixes for yw cosimJannis Harder2023-01-112-1/+13
| | | | | | | | | | | | * Fixed $cover handling * Improved sparse memory handling when writing traces * JSON summary output
| * Support for BTOR witness to Yosys witness conversionJannis Harder2023-01-112-12/+25
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| * aiger: Use new JSON code for writing aiger witness map filesJannis Harder2023-01-112-6/+47
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| * Add json.{h,cc} for pretty printing JSONJannis Harder2023-01-112-0/+222
| | | | | | | | | | | | Avoids errors in trailing comma handling, broken indentation and improper escaping that is common when building JSON by manually concatenating strings.
| * New kernel/yw.{h,cc} to support reading Yosys witness filesJannis Harder2023-01-112-0/+379
| | | | | | | | | | | | This contains parsing code as well as generic routines to associate the hierarchical signals paths within a Yosys witness file to a loaded RTLIL design, including support for memories.
| * xprop, setundef: Mark xprop decoding bwmuxes, exclude them from setundefJannis Harder2023-01-111-0/+1
| | | | | | | | | | | | | | | | This adds the xprop_decoder attribute to bwmuxes that drive the original unencoded signals. Setundef is changed to ignore the x inputs of these bwmuxes, so that they survive the prep script of SBY's formal flow. This is required to make simulation (via sim) using the prep model show the decoded x signals instead of 0/1 values made up by the solver.
* | Merge pull request #3629 from YosysHQ/micko/clang_fixesMiodrag Milanović2023-01-233-6/+7
|\ \ | | | | | | Fixes for some of clang scan-build detected issues
| * | Fixes for some of clang scan-build detected issuesMiodrag Milanovic2023-01-173-6/+7
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* / Call yosys_shutdown to properly cleanup plugins and tcl when expecting errorMiodrag Milanovic2023-01-201-0/+1
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* Merge pull request #3537 from jix/xpropJannis Harder2023-01-115-18/+121
|\ | | | | New xprop pass
| * Add bitwise `$bweqx` and `$bwmux` cellsJannis Harder2022-11-305-4/+112
| | | | | | | | | | | | The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`) cells enable compact encoding and decoding of 3-valued logic signals using multiple 2-valued signals.
| * satgen, simlib: Consistent x-propagation for `$pmux` cellsJannis Harder2022-11-301-14/+9
| | | | | | | | | | This updates satgen and simlib to use a `$pmux` model where the output is fully X when the S input is not all zero or one-hot with no x bits.
* | remove template declaration that stops function from being usedN. Engelhardt2023-01-111-4/+0
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* | Deprecate gcc-4.8Miodrag Milanovic2023-01-112-55/+18
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* | Display error instead of assertion when pass existsMiodrag Milanovic2023-01-091-5/+12
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* | add note to help about how to chain commandsN. Engelhardt2023-01-021-1/+1
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* | Remove help outputs for texKrystalDelusion2022-12-081-92/+0
| | | | | | | | Also for old website.
* | tcl: Update help message to mention 'tee -s'Jannis Harder2022-12-051-2/+2
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* | tcl: Unset both result.json and result.string only before calling passJannis Harder2022-12-051-2/+1
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* | tcl: Don't exit repl on recoverable command errorsJannis Harder2022-12-022-4/+36
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* | tcl: Return scratchpad result.json and result.string as tcl objectsJannis Harder2022-12-021-2/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This makes it possible for yosys commands to return values when invoked as tcl commands. Right now no commands natively support this, but the tee command can be used with json output like this: ```tcl set stat [yosys tee -q -s result.json stat -json -top top] dict get $stat modules \\top num_cells_by_type \$pmux ``` Or with newline separated lists like this: ```tcl split [yosys tee -q -s result.string select -list top] "\n" ```
* | tee: Allow logging command output to a given scratchpad valueJannis Harder2022-12-022-0/+7
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* | Fix tcl crash in case of error executing commandMiodrag Milanovic2022-11-302-1/+8
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* sat: Add -set-def-formal option to force defined $any* outputsJannis Harder2022-11-282-4/+24
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* Add TCL interactive shell modeMiodrag Milanovic2022-11-252-8/+34
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* Rst docs conversion (#3496)KrystalDelusion2022-11-151-0/+109
| | | Rst docs conversion
* Add missing memory width assert preventing division by zero (#3546)Emil J2022-11-091-0/+1
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* fstdata: Update past_data before end_time callbackJannis Harder2022-11-071-0/+1
| | | | Required to make the '-at' parameter work.
* fstdata: Handle square/angle bracket replacemnt, change memory handlingJannis Harder2022-11-071-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When writing VCDs smtbmc replaces square brackets with angle brackets to avoid the issues with VCD readers misinterpreting such signal names. For memory addresses it also uses angle brackets and hexadecimal addresses, while other tools will use square brackets and decimal addresses. Previously the code handled both forms of memory addresses, assuming that any signal that looks like a memory address is a memory address. This is not the case when the user uses regular signals whose names include square brackets _or_ when the verific frontend generates such names to represent various constructs. With this change all angular brackets are turned into square brackets when reading the trace _and_ when performing a signal lookup. This means no matter which kind of brackets are used in the design or in the VCD signals will be matched. This will not handle multiple signals that are the same apart from replacing square/angle brackets, but this will cause issues during the VCD writing of smtbmc already. It still uses the distinction between square and angle brackets for memories to decide whether the address is hex or decimal, but even if something looks like a memory and is added to the `memory_to_handle` data, the plain signal added to `name_to_handle` is used as-is, without rewriting the address. This last change is needed to successfully match verific generated signal names that look like memory addresses while keeping memories working at the same time. It may cause regressions when VCD generation was done with a design that had memories but simulation is done with a design where the memories were mapped to registers. This seems like an unusual setup, but could be worked around with some further changes should this be required.
* Add missing log_dump_val_worker forward declarationsClaire Xenia Wolf2022-10-301-0/+5
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Consistent $mux undef handlingJannis Harder2022-10-243-10/+36
| | | | | | | | | | | | | | | | | | | * Change simlib's $mux cell to use the ternary operator as $_MUX_ already does * Stop opt_expr -keepdc from changing S=x to S=0 * Change const eval of $mux and $pmux to match the updated simlib (fixes sim) * The sat behavior of $mux already matches the updated simlib The verilog frontend uses $mux for the ternary operators and this changes all interpreations of the $mux cell (that I found) to match the verilog simulation behavior for the ternary operator. For 'if' and 'case' expressions the frontend may also use $mux but uses $eqx if the verilog simulation behavior is requested with the '-ifx' option. For $pmux there is a remaining mismatch between the sat behavior and the simlib behavior. Resolving this requires more discussion, as the $pmux cell does not directly correspond to a specific verilog construct.
* Add missing log_dump handler for std::vector<>Claire Xenia Wolf2022-10-201-0/+12
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.Jannis Harder2022-10-071-0/+3
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* Fix mingw buildMiodrag Milanovic2022-08-291-0/+3
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* kernel: hashlib: cleaned up message about table size in cases where ↵Aki Van Ness2022-08-251-1/+1
| | | | `sizeof(int) == 4`, (closes #3440)
* use inttypes format specifiersN. Engelhardt2022-08-251-3/+3
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* dump runtime information for passes to jsonN. Engelhardt2022-08-251-1/+28
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* formalff: Set new replaced_by_gclk attribute on removed dff's clksJannis Harder2022-08-161-0/+1
| | | | | | This attribute can be used by formal backends to indicate which clocks were mapped to the global clock. Update the btor and smt2 backend which already handle clock inputs to understand this attribute.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-166-6/+48
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Encode filename unprintable charsMiodrag Milanovic2022-08-081-0/+15
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* Assorted microoptimization speedups in core data structures.Marcelina Kościelnicka2022-07-276-193/+117
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* Make all compile under OpenBSD (#3423)Miodrag Milanović2022-07-272-0/+42
| | | Co-authored-by: Josuah Demangeon <me@josuah.net>
* Merge pull request #3392 from rockybulwinkle/rockybulwinkle-patch-1Miodrag Milanović2022-07-111-0/+4
|\ | | | | Update tcl doc, yosys does not return data to tcl
| * Remove empty linesMarcelina Kościelnicka2022-07-111-2/+0
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| * Update tcl doc, yosys does not return data to tclrockybulwinkle2022-06-231-0/+6
| | | | | | | | | | | | | | This pull request is to address YosysHQ/yosys#2980. The documentation, as originally written, does not make it clear that yosys commands, when used within a tcl script, do not return any value to the tcl script. This pull request notes this and offers a workaround via tee as noted in the issue.
* | using more portable formattingMiodrag Milanovic2022-07-061-1/+1
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