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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-07 12:52:03 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-08 10:52:08 -0800 |
| commit | a63e2508fcca395e795029d5c57c59acc63a9959 (patch) | |
| tree | c28d4800477a6fba3adb45f15ec2ae2168ffef56 /kernel | |
| parent | 823a08e0d8272e8d48584eecc2d8dc57bdb98a6e (diff) | |
| download | yosys-a63e2508fcca395e795029d5c57c59acc63a9959.tar.gz yosys-a63e2508fcca395e795029d5c57c59acc63a9959.tar.bz2 yosys-a63e2508fcca395e795029d5c57c59acc63a9959.zip | |
Add RTLIL::constpad, init by yosys_setup(); use for abc9
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 1 | ||||
| -rw-r--r-- | kernel/rtlil.h | 2 | ||||
| -rw-r--r-- | kernel/yosys.cc | 9 |
3 files changed, 12 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ab4f4f377..f286d139f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -46,6 +46,7 @@ IdString RTLIL::ID::Y; IdString RTLIL::ID::keep; IdString RTLIL::ID::whitebox; IdString RTLIL::ID::blackbox; +dict<std::string, std::string> RTLIL::constpad; RTLIL::Const::Const() { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index e5b24cc02..6251d265d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -377,6 +377,8 @@ namespace RTLIL extern IdString blackbox; }; + extern dict<std::string, std::string> constpad; + static inline std::string escape_id(std::string str) { if (str.size() > 0 && str[0] != '\\' && str[0] != '$') return "\\" + str; diff --git a/kernel/yosys.cc b/kernel/yosys.cc index 5018a4888..6c8427c19 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -524,6 +524,15 @@ void yosys_setup() PyRun_SimpleString("import sys"); #endif + RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -v; &mfs"; + RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} -a -v; &mfs"; + RTLIL::constpad["abc9.script.default.fast"] = "&if {W} {D}"; + RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \ + "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} -v; &save; &load; "\ + "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} -v; &save; &load; "\ + "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} -v; &save; &load; "\ + "&mfs"; + Pass::init_register(); yosys_design = new RTLIL::Design; yosys_celltypes.setup(); |