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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 19:35:23 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-29 19:35:23 -0700 |
| commit | d5f0794a531b36976d2c4d181b1c3921b801bbfa (patch) | |
| tree | 8796974703b6f343bc1c579b1d90de94f14a38e8 /kernel | |
| parent | 8474c5b366660153cae03a9de4af8e1ed809856d (diff) | |
| parent | 8c2b4f0a50678f949418b7b7329550615fadde83 (diff) | |
| download | yosys-d5f0794a531b36976d2c4d181b1c3921b801bbfa.tar.gz yosys-d5f0794a531b36976d2c4d181b1c3921b801bbfa.tar.bz2 yosys-d5f0794a531b36976d2c4d181b1c3921b801bbfa.zip | |
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
Avoid work in replace() if rules empty.
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1d380135b..17be28f78 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3083,6 +3083,7 @@ void RTLIL::SigSpec::replace(const dict<RTLIL::SigBit, RTLIL::SigBit> &rules, RT log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); @@ -3107,6 +3108,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules log_assert(other != NULL); log_assert(width_ == other->width_); + if (rules.empty()) return; unpack(); other->unpack(); |