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* Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-272-1/+6
* Update CopyrightClaire Wolf2020-03-161-1/+1
* License: bump year and add titleWaldir Pimenta2020-03-141-1/+1
* exclude clang from checkingMiodrag Milanovic2020-03-131-1/+1
* Add YS_ prefix to macros, add explanation and apply to older version as wellMiodrag Milanovic2020-03-133-20/+23
* Use boost xpressive for gcc 4.8Miodrag Milanovic2020-03-133-23/+29
* Fix compilation for emccjiegec2020-03-112-1/+4
* Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-092-0/+13
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+0
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| * Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-231-2/+0
* | Small fixesEddie Hung2020-02-271-2/+2
* | Fixes for older compilersEddie Hung2020-02-271-1/+8
* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-4/+5
* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-9/+19
* | Fix spacingEddie Hung2020-02-271-50/+50
* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-3/+4
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-1/+4
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-18/+2
* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-0/+173
* | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-263-2/+100
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| * Remove duplicate warning detectionMiodrag Milanovic2020-02-231-0/+6
| * Handle expect no warnings together with expectedMiodrag Milanovic2020-02-223-4/+12
| * Prevent double error messageMiodrag Milanovic2020-02-171-1/+3
| * Option to expect no warningsMiodrag Milanovic2020-02-173-0/+5
| * No new error if already failingMiodrag Milanovic2020-02-171-1/+2
| * remove whitespaceMiodrag Milanovic2020-02-141-1/+1
| * Add expect option to logger commandMiodrag Milanovic2020-02-143-2/+78
* | specify: system timing checks to accept min:typ:max tripleEddie Hung2020-02-131-2/+6
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* Merge pull request #1659 from YosysHQ/clifford/experimentalClaire Wolf2020-01-295-3/+55
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| * Improve logging use of experimental featuresClaire Wolf2020-01-283-4/+8
| * Add log_experimental() and experimental() API and "yosys -x"Claire Wolf2020-01-275-3/+51
* | Add and use SigSpec::reverse()Eddie Hung2020-01-281-0/+2
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* Merge pull request #1613 from porglezomp-misc/version-flag-aliasClaire Wolf2020-01-271-0/+6
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| * Add --version and -version as aliases for -VCassie Jones2020-01-051-0/+6
* | As before, only display MEM if Linux or FreeBSDEddie Hung2020-01-141-3/+7
* | print_stats footer to return peak memory, option for including childrenEddie Hung2020-01-141-28/+12
* | Move abc9.* constpad entries to Abc9Pass::on_register()Eddie Hung2020-01-091-35/+0
* | Merge remote-tracking branch 'origin/clifford/onpassreg' into eddie/abc9_scra...Eddie Hung2020-01-093-1/+20
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| * | Add Pass::on_register() and Pass::on_shutdown()Clifford Wolf2020-01-093-1/+20
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* | Add abc9.if.script.flow{,2} to constpadEddie Hung2020-01-081-6/+32
* | Add RTLIL::constpad, init by yosys_setup(); use for abc9Eddie Hung2020-01-083-0/+12
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* Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputsClifford Wolf2020-01-021-4/+25
* kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.whitequark2019-12-041-3/+21
* Fix for SigSpec() == SigSpec(State::Sx, 0) to be true againEddie Hung2019-10-041-0/+6
* Add Const::{begin,end,empty}()Eddie Hung2019-10-041-0/+3
* log_dump() to support State enumEddie Hung2019-10-023-0/+6
* Fix typoEddie Hung2019-09-301-1/+1
* Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_inMiodrag Milanović2019-09-302-3/+3
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| * Open aig frontend as binary fileMiodrag Milanovic2019-09-292-3/+3
* | Merge pull request #1414 from hzeller/improve-replace-with-empty-mapEddie Hung2019-09-291-0/+2
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