iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Renamed extend() to extend_xx(), changed most users to extend_u0()	Clifford Wolf	2014-12-24	1	-8/+7
*	Added IdString::destruct_guard hack	Clifford Wolf	2014-12-11	1	-0/+1
*	Added bool constructors to SigBit and SigSpec	Clifford Wolf	2014-12-08	1	-0/+10
*	Added module->addDffe() and module->addDffeGate()	Clifford Wolf	2014-12-08	1	-1/+24
*	Added $dffe cell type	Clifford Wolf	2014-12-08	1	-0/+11
*	Added $_DFFE_??_ cell types	Clifford Wolf	2014-12-08	1	-0/+5
*	Added log_warning() API	Clifford Wolf	2014-11-09	1	-3/+3
*	Added support for $readmemh/$readmemb	Clifford Wolf	2014-10-26	1	-1/+1
*	Fixed various VS warnings	Clifford Wolf	2014-10-18	1	-2/+2
*	Various win32 / vs build fixes	Clifford Wolf	2014-10-17	1	-1/+1
*	Fixed RTLIL::SigSpec::parse() for out-of-range bit- and part-selects	Clifford Wolf	2014-10-16	1	-1/+8
*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-29/+29
*	Added $_BUF_ cell type	Clifford Wolf	2014-10-03	1	-0/+1
*	Initialize RTLIL::Const from std::vector<bool>	Clifford Wolf	2014-09-19	1	-0/+7
*	Fixed monitor notifications for removed cell	Clifford Wolf	2014-09-14	1	-0/+3
*	Added $lcu cell type	Clifford Wolf	2014-09-08	1	-0/+14
*	Added "$fa" cell type	Clifford Wolf	2014-09-08	1	-0/+15
*	Added $macc cell type	Clifford Wolf	2014-09-06	1	-1/+13
*	Removed $bu0 cell type	Clifford Wolf	2014-09-04	1	-2/+1
*	Create a default selection stack in RTLIL::Design::Design()	Clifford Wolf	2014-09-02	1	-0/+1
*	Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::...	Clifford Wolf	2014-09-01	1	-33/+29
*	Added $lut support in test_cell, techmap, satgen	Clifford Wolf	2014-08-31	1	-3/+7
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-0/+61
*	Added $alu cell type	Clifford Wolf	2014-08-30	1	-0/+14
*	Fixed module->addPmux()	Clifford Wolf	2014-08-30	1	-1/+0
*	Added is_signed argument to SigSpec.as_int() and Const.as_int()	Clifford Wolf	2014-08-24	1	-4/+7
*	Changed backend-api from FILE to std::ostream	Clifford Wolf	2014-08-23	1	-8/+3
*	Added emscripten (emcc) support to build system and some build fixes	Clifford Wolf	2014-08-22	1	-0/+4
*	Added mod->addGate() methods for new gate types	Clifford Wolf	2014-08-19	1	-53/+76
*	Improved sig.remove2() performance	Clifford Wolf	2014-08-17	1	-2/+11
*	Added module->uniquify()	Clifford Wolf	2014-08-16	1	-0/+22
*	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $...	Clifford Wolf	2014-08-16	1	-5/+12
*	Renamed $lut ports to follow A-Y naming scheme	Clifford Wolf	2014-08-15	1	-4/+4
*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-2/+2
*	Added RTLIL::SigSpec::to_sigbit_map()	Clifford Wolf	2014-08-14	1	-0/+16
*	Added sig.{replace,remove,extract} variants for std::{map,set} pattern	Clifford Wolf	2014-08-14	1	-24/+53
*	Added module->ports	Clifford Wolf	2014-08-14	1	-1/+9
*	Refactoring of CellType class	Clifford Wolf	2014-08-14	1	-10/+6
*	RIP $safe_pmux	Clifford Wolf	2014-08-14	1	-4/+3
*	Added support for truncating of wires to wreduce pass	Clifford Wolf	2014-08-05	1	-0/+30
*	Bugfix in "techmap -extern"	Clifford Wolf	2014-08-02	1	-10/+16
*	Removed at() method from RTLIL::IdString	Clifford Wolf	2014-08-02	1	-2/+2
*	No implicit conversion from IdString to anything else	Clifford Wolf	2014-08-02	1	-14/+14
*	Improvements in new RTLIL::IdString implementation	Clifford Wolf	2014-08-02	1	-2/+2
*	Implemented new reference counting RTLIL::IdString	Clifford Wolf	2014-08-02	1	-2/+6
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Added ModIndex helper class, some changes to RTLIL::Monitor	Clifford Wolf	2014-08-01	1	-13/+23
*	Packed SigBit::data and SigBit::offset in a union	Clifford Wolf	2014-08-01	1	-1/+3
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-82/+102
*	Added RTLIL::Monitor	Clifford Wolf	2014-07-31	1	-94/+79