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| author | Clifford Wolf <clifford@clifford.at> | 2014-12-08 10:50:19 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-12-08 10:50:19 +0100 |
| commit | f1764b4fe99807c445526774563a98224b642766 (patch) | |
| tree | 8acab5d97a8f973b75b258036923b209446a9139 /kernel/rtlil.cc | |
| parent | fad9cec47b3aa9fc3d413abee92cc8380d0c0dc4 (diff) | |
| download | yosys-f1764b4fe99807c445526774563a98224b642766.tar.gz yosys-f1764b4fe99807c445526774563a98224b642766.tar.bz2 yosys-f1764b4fe99807c445526774563a98224b642766.zip | |
Added $dffe cell type
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 321c39e10..b1bf43941 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -752,6 +752,17 @@ namespace { return; } + if (cell->type == "$dffe") { + param_bool("\\CLK_POLARITY"); + param_bool("\\EN_POLARITY"); + port("\\CLK", 1); + port("\\EN", 1); + port("\\D", param("\\WIDTH")); + port("\\Q", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$dffsr") { param_bool("\\CLK_POLARITY"); param_bool("\\SET_POLARITY"); |