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author | Clifford Wolf <clifford@clifford.at> | 2014-08-14 23:14:47 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-14 23:14:47 +0200 |
commit | 978a933b6af8863200096bd3a56780e3378e4848 (patch) | |
tree | b6f2dbb89c50c3f6c35098aa8ecff4c20675a52f /kernel/rtlil.cc | |
parent | c83b9904582b81e71c4c510ffdc26f9796f5da21 (diff) | |
download | yosys-978a933b6af8863200096bd3a56780e3378e4848.tar.gz yosys-978a933b6af8863200096bd3a56780e3378e4848.tar.bz2 yosys-978a933b6af8863200096bd3a56780e3378e4848.zip |
Added RTLIL::SigSpec::to_sigbit_map()
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 297537f00..f4f32f600 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2687,6 +2687,22 @@ std::vector<RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_vector() const return bits_; } +std::map<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_map(const RTLIL::SigSpec &other) const +{ + cover("kernel.rtlil.sigspec.to_sigbit_map"); + + unpack(); + other.unpack(); + + log_assert(width_ == other.width_); + + std::map<RTLIL::SigBit, RTLIL::SigBit> new_map; + for (int i = 0; i < width_; i++) + new_map[bits_[i]] = other.bits_[i]; + + return new_map; +} + RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const { cover("kernel.rtlil.sigspec.to_single_sigbit"); |