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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-08 13:28:23 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-08 13:31:04 +0200 |
| commit | af0c8873bbc13eea10b3d705061b4cf68fe27c17 (patch) | |
| tree | a295ce024870762e0388cd9fcd28c458d86fa0d3 /kernel/rtlil.cc | |
| parent | 48b00dcceab8bb046258cd6f0912636a6e5b232c (diff) | |
| download | yosys-af0c8873bbc13eea10b3d705061b4cf68fe27c17.tar.gz yosys-af0c8873bbc13eea10b3d705061b4cf68fe27c17.tar.bz2 yosys-af0c8873bbc13eea10b3d705061b4cf68fe27c17.zip | |
Added $lcu cell type
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index b5cede8b2..ec4375f2f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -630,6 +630,15 @@ namespace { return; } + if (cell->type == "$lcu") { + port("\\P", param("\\WIDTH")); + port("\\G", param("\\WIDTH")); + port("\\CI", 1); + port("\\CO", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$alu") { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); @@ -1808,6 +1817,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } + if (type == "$lcu") { + parameters["\\WIDTH"] = SIZE(connections_["\\CO"]); + return; + } + bool signedness_ab = !type.in("$slice", "$concat", "$macc"); if (connections_.count("\\A")) { |