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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-02 22:49:24 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-02 22:49:24 +0200 |
| commit | da360771a193707b59eac9b95b3bfe1652a057aa (patch) | |
| tree | 8f09645fbab743bfe8b0246584d29b007f674a70 /kernel/rtlil.cc | |
| parent | c38283dbd033ba95554600bbaa850de707ab2a78 (diff) | |
| download | yosys-da360771a193707b59eac9b95b3bfe1652a057aa.tar.gz yosys-da360771a193707b59eac9b95b3bfe1652a057aa.tar.bz2 yosys-da360771a193707b59eac9b95b3bfe1652a057aa.zip | |
Create a default selection stack in RTLIL::Design::Design()
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f237f57ef..35cd54b46 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -228,6 +228,7 @@ void RTLIL::Selection::optimize(RTLIL::Design *design) RTLIL::Design::Design() { refcount_modules_ = 0; + selection_stack.push_back(RTLIL::Selection()); } RTLIL::Design::~Design() |