Renamed SIZE() to GetSize() because of name collision on Win32

1 files changed, 29 insertions, 29 deletions

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 89132ea29..28f0dfdc5 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -941,10 +941,10 @@ void RTLIL::Module::check()
 		for (auto &it2 : it.second->attributes)
 			log_assert(!it2.first.empty());
 		if (it.second->port_id) {
-			log_assert(SIZE(ports) >= it.second->port_id);
+			log_assert(GetSize(ports) >= it.second->port_id);
 			log_assert(ports.at(it.second->port_id-1) == it.first);
 			log_assert(it.second->port_input || it.second->port_output);
-			if (SIZE(ports_declared) < it.second->port_id)
+			if (GetSize(ports_declared) < it.second->port_id)
 				ports_declared.resize(it.second->port_id);
 			log_assert(ports_declared[it.second->port_id-1] == false);
 			ports_declared[it.second->port_id-1] = true;
@@ -953,7 +953,7 @@ void RTLIL::Module::check()
 	}
 	for (auto port_declared : ports_declared)
 		log_assert(port_declared == true);
-	log_assert(SIZE(ports) == SIZE(ports_declared));
+	log_assert(GetSize(ports) == GetSize(ports_declared));
 
 	for (auto &it : memories) {
 		log_assert(it.first == it.second->name);
@@ -1811,25 +1811,25 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 		return;
 
 	if (type == "$mux" || type == "$pmux") {
-		parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+		parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
 		if (type == "$pmux")
-			parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
+			parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
 		check();
 		return;
 	}
 
 	if (type == "$lut") {
-		parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
+		parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
 		return;
 	}
 
 	if (type == "$fa") {
-		parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+		parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
 		return;
 	}
 
 	if (type == "$lcu") {
-		parameters["\\WIDTH"] = SIZE(connections_["\\CO"]);
+		parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
 		return;
 	}
 
@@ -1842,7 +1842,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 			else if (parameters.count("\\A_SIGNED") == 0)
 				parameters["\\A_SIGNED"] = false;
 		}
-		parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
+		parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
 	}
 
 	if (connections_.count("\\B")) {
@@ -1852,11 +1852,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 			else if (parameters.count("\\B_SIGNED") == 0)
 				parameters["\\B_SIGNED"] = false;
 		}
-		parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
+		parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
 	}
 
 	if (connections_.count("\\Y"))
-		parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
+		parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
 
 	check();
 }
@@ -1872,7 +1872,7 @@ RTLIL::SigChunk::SigChunk(const RTLIL::Const &value)
 {
 	wire = NULL;
 	data = value.bits;
-	width = SIZE(data);
+	width = GetSize(data);
 	offset = 0;
 }
 
@@ -1896,7 +1896,7 @@ RTLIL::SigChunk::SigChunk(const std::string &str)
 {
 	wire = NULL;
 	data = RTLIL::Const(str).bits;
-	width = SIZE(data);
+	width = GetSize(data);
 	offset = 0;
 }
 
@@ -1904,7 +1904,7 @@ RTLIL::SigChunk::SigChunk(int val, int width)
 {
 	wire = NULL;
 	data = RTLIL::Const(val, width).bits;
-	this->width = SIZE(data);
+	this->width = GetSize(data);
 	offset = 0;
 }
 
@@ -1912,7 +1912,7 @@ RTLIL::SigChunk::SigChunk(RTLIL::State bit, int width)
 {
 	wire = NULL;
 	data = RTLIL::Const(bit, width).bits;
-	this->width = SIZE(data);
+	this->width = GetSize(data);
 	offset = 0;
 }
 
@@ -2258,7 +2258,7 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec
 
 	std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
 
-	for (int i = 0; i < SIZE(pattern.bits_); i++)
+	for (int i = 0; i < GetSize(pattern.bits_); i++)
 		if (pattern.bits_[i].wire != NULL)
 			rules[pattern.bits_[i]] = with.bits_[i];
 
@@ -2280,7 +2280,7 @@ void RTLIL::SigSpec::replace(const std::map<RTLIL::SigBit, RTLIL::SigBit> &rules
 	unpack();
 	other->unpack();
 
-	for (int i = 0; i < SIZE(bits_); i++) {
+	for (int i = 0; i < GetSize(bits_); i++) {
 		auto it = rules.find(bits_[i]);
 		if (it != rules.end())
 			other->bits_[i] = it->second;
@@ -2333,12 +2333,12 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
 
 	std::vector<RTLIL::SigBit> new_bits, new_other_bits;
 
-	new_bits.resize(SIZE(bits_));
+	new_bits.resize(GetSize(bits_));
 	if (other != NULL)
-		new_other_bits.resize(SIZE(bits_));
+		new_other_bits.resize(GetSize(bits_));
 
 	int k = 0;
-	for (int i = 0; i < SIZE(bits_); i++) {
+	for (int i = 0; i < GetSize(bits_); i++) {
 		if (bits_[i].wire != NULL && pattern.count(bits_[i]))
 			continue;
 		if (other != NULL)
@@ -2351,11 +2351,11 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
 		new_other_bits.resize(k);
 
 	bits_.swap(new_bits);
-	width_ = SIZE(bits_);
+	width_ = GetSize(bits_);
 
 	if (other != NULL) {
 		other->bits_.swap(new_other_bits);
-		other->width_ = SIZE(other->bits_);
+		other->width_ = GetSize(other->bits_);
 	}
 
 	check();
@@ -2418,7 +2418,7 @@ void RTLIL::SigSpec::remove_const()
 		cover("kernel.rtlil.sigspec.remove_const.packed");
 
 		std::vector<RTLIL::SigChunk> new_chunks;
-		new_chunks.reserve(SIZE(chunks_));
+		new_chunks.reserve(GetSize(chunks_));
 
 		width_ = 0;
 		for (auto &chunk : chunks_)
@@ -2624,7 +2624,7 @@ void RTLIL::SigSpec::check() const
 	{
 		cover("kernel.rtlil.sigspec.check.unpacked");
 
-		log_assert(width_ == SIZE(bits_));
+		log_assert(width_ == GetSize(bits_));
 		log_assert(chunks_.empty());
 	}
 }
@@ -2699,7 +2699,7 @@ bool RTLIL::SigSpec::is_wire() const
 	cover("kernel.rtlil.sigspec.is_wire");
 
 	pack();
-	return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
+	return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
 }
 
 bool RTLIL::SigSpec::is_chunk() const
@@ -2707,7 +2707,7 @@ bool RTLIL::SigSpec::is_chunk() const
 	cover("kernel.rtlil.sigspec.is_chunk");
 
 	pack();
-	return SIZE(chunks_) == 1;
+	return GetSize(chunks_) == 1;
 }
 
 bool RTLIL::SigSpec::is_fully_const() const
@@ -2770,7 +2770,7 @@ bool RTLIL::SigSpec::as_bool() const
 	cover("kernel.rtlil.sigspec.as_bool");
 
 	pack();
-	log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+	log_assert(is_fully_const() && GetSize(chunks_) <= 1);
 	if (width_)
 		return RTLIL::Const(chunks_[0].data).as_bool();
 	return false;
@@ -2781,7 +2781,7 @@ int RTLIL::SigSpec::as_int(bool is_signed) const
 	cover("kernel.rtlil.sigspec.as_int");
 
 	pack();
-	log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+	log_assert(is_fully_const() && GetSize(chunks_) <= 1);
 	if (width_)
 		return RTLIL::Const(chunks_[0].data).as_int(is_signed);
 	return 0;
@@ -2809,7 +2809,7 @@ RTLIL::Const RTLIL::SigSpec::as_const() const
 	cover("kernel.rtlil.sigspec.as_const");
 
 	pack();
-	log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+	log_assert(is_fully_const() && GetSize(chunks_) <= 1);
 	if (width_)
 		return chunks_[0].data;
 	return RTLIL::Const();