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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-08 12:15:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-08 12:15:39 +0200 |
| commit | d46bac330520f91ee5bf8027abe98a8f9389f696 (patch) | |
| tree | d1b87a2409d082fa281d2c9ea100e94c69a43912 /kernel/rtlil.cc | |
| parent | 1a88e47396305bd6b5ee2a7a91a1d014ebd37c10 (diff) | |
| download | yosys-d46bac330520f91ee5bf8027abe98a8f9389f696.tar.gz yosys-d46bac330520f91ee5bf8027abe98a8f9389f696.tar.bz2 yosys-d46bac330520f91ee5bf8027abe98a8f9389f696.zip | |
Added "$fa" cell type
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 97a2946a6..b5cede8b2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -620,6 +620,16 @@ namespace { return; } + if (cell->type == "$fa") { + port("\\A", param("\\WIDTH")); + port("\\B", param("\\WIDTH")); + port("\\C", param("\\WIDTH")); + port("\\X", param("\\WIDTH")); + port("\\Y", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$alu") { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); @@ -1793,6 +1803,11 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) return; } + if (type == "$fa") { + parameters["\\WIDTH"] = SIZE(connections_["\\Y"]); + return; + } + bool signedness_ab = !type.in("$slice", "$concat", "$macc"); if (connections_.count("\\A")) { |