| Commit message (Expand) | Author | Age | Files | Lines |
* | set default_nettype to wire for resetall | Miodrag Milanovic | 2022-08-10 | 1 | -0/+1 |
* | resetall does not affect text defines, but undefineall does | Miodrag Milanovic | 2022-08-10 | 1 | -0/+4 |
* | verilog: support for time scale delay values | Zachary Snow | 2022-02-14 | 2 | -4/+16 |
* | preprocessor: do not destroy double slash escaped identifiers | Thomas Sailer | 2021-12-15 | 1 | -0/+10 |
* | Specify minimum bison version 3.0+ | Zachary Snow | 2021-10-01 | 1 | -0/+2 |
* | Merge pull request #3014 from YosysHQ/claire/fix-vgtest | Claire Xen | 2021-09-24 | 1 | -0/+1 |
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| * | Fix TOK_ID memory leak in for_initialization | Zachary Snow | 2021-09-23 | 1 | -0/+1 |
* | | sv: support wand and wor of data types | Zachary Snow | 2021-09-21 | 1 | -9/+12 |
* | | verilog: fix multiple AST_PREFIX scope resolution issues | Zachary Snow | 2021-09-21 | 1 | -0/+1 |
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* | verilog: Squash flex-triggered warning. | Marcelina Kościelnicka | 2021-09-13 | 1 | -0/+2 |
* | sv: support declaration in generate for initialization | Zachary Snow | 2021-08-31 | 1 | -1/+95 |
* | sv: support declaration in procedural for initialization | Zachary Snow | 2021-08-30 | 1 | -1/+48 |
* | sv: improve support for wire and var with user-defined types | Brett Witherspoon | 2021-08-12 | 1 | -11/+44 |
* | Allow optional comma after last entry in enum | Michael Singer | 2021-08-09 | 1 | -11/+12 |
* | verilog: Support tri/triand/trior wire types. | Marcelina Kościelnicka | 2021-08-06 | 1 | -0/+3 |
* | verilog: save and restore overwritten macro arguments | Zachary Snow | 2021-07-28 | 2 | -4/+31 |
* | Add support for parsing the SystemVerilog 'bind' construct | Rupert Swarbrick | 2021-07-16 | 2 | -3/+75 |
* | sv: fix a few struct and enum memory leaks | Zachary Snow | 2021-07-06 | 1 | -2/+4 |
* | sv: fix up end label checking | Zachary Snow | 2021-06-16 | 1 | -7/+18 |
* | verilog: fix leaking of type names in parser | Xiretza | 2021-06-14 | 1 | -0/+2 |
* | verilog: fix wildcard port connections leaking memory | Xiretza | 2021-06-14 | 1 | -0/+1 |
* | verilog: fix leaking ASTNodes | Xiretza | 2021-06-14 | 1 | -7/+10 |
* | verilog: Squash a memory leak. | Marcelina Kościelnicka | 2021-06-14 | 4 | -19/+14 |
* | Fixing old e-mail addresses and deadnames | Claire Xenia Wolf | 2021-06-08 | 7 | -7/+7 |
* | sv: support tasks and functions within packages | Zachary Snow | 2021-06-01 | 1 | -1/+1 |
* | sv: support remaining assignment operators | Zachary Snow | 2021-05-25 | 2 | -42/+41 |
* | sv: check validity of package end label | Zachary Snow | 2021-05-10 | 1 | -0/+2 |
* | verilog: revise hot comment warnings | Zachary Snow | 2021-03-30 | 1 | -6/+21 |
* | preproc: Fix up conditional handling. | Marcelina Kościelnicka | 2021-03-30 | 1 | -3/+17 |
* | verilog: check entire user type stack for type definition | Xiretza | 2021-03-21 | 1 | -6/+12 |
* | sv: allow typenames as function return types | Zachary Snow | 2021-03-19 | 1 | -0/+6 |
* | verilog: rebuild user_type_stack from globals before parsing file | Xiretza | 2021-03-18 | 1 | -5/+21 |
* | sv: carry over global typedefs from previous files | Zachary Snow | 2021-03-17 | 1 | -2/+5 |
* | sv: support for parameters without default values | Zachary Snow | 2021-03-02 | 1 | -3/+21 |
* | verilog: fix sizing of ports with int types in module headers | Zachary Snow | 2021-03-01 | 1 | -2/+3 |
* | verilog: fix handling of nested ifdef directives | Zachary Snow | 2021-03-01 | 1 | -11/+38 |
* | Merge pull request #2523 from tomverbeure/define_synthesis | Claire Xen | 2021-03-01 | 1 | -3/+12 |
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| * | Fix indents. | Tom Verbeure | 2021-01-04 | 1 | -2/+2 |
| * | Add -nosynthesis flag for read_verilog command. | Tom Verbeure | 2021-01-04 | 1 | -3/+12 |
* | | sv: extended support for integer types | Zachary Snow | 2021-02-28 | 2 | -39/+70 |
* | | Fix handling of unique/unique0/priority cases in the frontend. | Marcelina Kościelnicka | 2021-02-25 | 2 | -15/+16 |
* | | Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and tu... | TimRudy | 2021-02-24 | 1 | -2/+7 |
* | | verilog: error on macro invocations with missing argument lists | Zachary Snow | 2021-02-19 | 1 | -1/+10 |
* | | Merge pull request #2578 from zachjs/genblk-port | Zachary Snow | 2021-02-11 | 1 | -4/+7 |
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| * | | verlog: allow shadowing module ports within generate blocks | Zachary Snow | 2021-02-07 | 1 | -4/+7 |
* | | | Add missing is_signed to type_atom | Kamil Rakoczy | 2021-02-11 | 1 | -4/+4 |
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* | | Add check of begin/end labels for genblock | Kamil Rakoczy | 2021-02-04 | 1 | -0/+2 |
* | | Merge pull request #2529 from zachjs/unnamed-genblk | whitequark | 2021-02-04 | 1 | -17/+28 |
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| * | | verilog: significant block scoping improvements | Zachary Snow | 2021-01-31 | 1 | -17/+28 |
* | | | verilog: strip leading and trailing spaces in macro args | Zachary Snow | 2021-01-28 | 1 | -1/+5 |
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