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| author | Xiretza <xiretza@xiretza.xyz> | 2021-03-18 10:38:36 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-14 13:56:51 -0400 |
| commit | b57e47fad8b4ecd5438ee49c618fc8978a4bb058 (patch) | |
| tree | 73f6363ebdc0b6683c52ccd5c1a864d76fc42e70 /frontends/verilog | |
| parent | 62a42c317c41590b654f59851b4730c89bfcd7ae (diff) | |
| download | yosys-b57e47fad8b4ecd5438ee49c618fc8978a4bb058.tar.gz yosys-b57e47fad8b4ecd5438ee49c618fc8978a4bb058.tar.bz2 yosys-b57e47fad8b4ecd5438ee49c618fc8978a4bb058.zip | |
verilog: fix wildcard port connections leaking memory
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4e601b51d..7d750ea28 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -2084,6 +2084,7 @@ cell_port: if (!sv_mode) frontend_verilog_yyerror("Wildcard port connections are only supported in SystemVerilog mode."); astbuf2->attributes[ID::wildcard_port_conns] = AstNode::mkconst_int(1, false); + free_attr($1); }; always_comb_or_latch: |