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| author | Zachary Snow <zach@zachjs.com> | 2021-03-01 13:31:25 -0500 |
|---|---|---|
| committer | Zachary Snow <zach@zachjs.com> | 2021-03-01 13:39:05 -0500 |
| commit | 10a6bc9b81d1c2236e80a608778c904aebe54c28 (patch) | |
| tree | bc9d0dd7f4893a2a132a7672e5a7f57db1a72726 /frontends/verilog | |
| parent | 1ec5994100510d6fb9e18ff7234ede496f831a51 (diff) | |
| download | yosys-10a6bc9b81d1c2236e80a608778c904aebe54c28.tar.gz yosys-10a6bc9b81d1c2236e80a608778c904aebe54c28.tar.bz2 yosys-10a6bc9b81d1c2236e80a608778c904aebe54c28.zip | |
verilog: fix sizing of ports with int types in module headers
Declaring the ports as standard module items already worked as expected.
This adds a missing usage of `checkRange()` so that headers such as
`module m(output integer x);` now work correctly.
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 476ee68ad..bcba9b76a 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -546,8 +546,9 @@ module_arg: node->str = *$4; SET_AST_NODE_LOC(node, @4, @4); node->port_id = ++port_counter; - if ($3 != NULL) - node->children.push_back($3); + AstNode *range = checkRange(node, $3); + if (range != NULL) + node->children.push_back(range); if (!node->is_input && !node->is_output) frontend_verilog_yyerror("Module port `%s' is neither input nor output.", $4->c_str()); if (node->is_reg && node->is_input && !node->is_output && !sv_mode) |