diff options
| author | Xiretza <xiretza@xiretza.xyz> | 2021-03-16 16:43:03 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-14 13:56:51 -0400 |
| commit | 091295a5a533c44a4ad20d297fdad1ec2a77903c (patch) | |
| tree | efb3ade270c1beafa74c22c4084b738e0d8375f3 /frontends/verilog | |
| parent | 9ca5a91724e114ebb8c04be8edfc0f2f5e8073a9 (diff) | |
| download | yosys-091295a5a533c44a4ad20d297fdad1ec2a77903c.tar.gz yosys-091295a5a533c44a4ad20d297fdad1ec2a77903c.tar.bz2 yosys-091295a5a533c44a4ad20d297fdad1ec2a77903c.zip | |
verilog: fix leaking ASTNodes
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/verilog_parser.y | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 3f4bf5bfd..4e601b51d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -503,18 +503,19 @@ optional_comma: module_arg_opt_assignment: '=' expr { if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { - AstNode *wire = new AstNode(AST_IDENTIFIER); - wire->str = ast_stack.back()->children.back()->str; if (ast_stack.back()->children.back()->is_input) { AstNode *n = ast_stack.back()->children.back(); if (n->attributes.count(ID::defaultvalue)) delete n->attributes.at(ID::defaultvalue); n->attributes[ID::defaultvalue] = $2; - } else - if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic) - ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); - else - ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); + } else { + AstNode *wire = new AstNode(AST_IDENTIFIER); + wire->str = ast_stack.back()->children.back()->str; + if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic) + ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); + else + ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); + } } else frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value."); } | @@ -1158,6 +1159,8 @@ specify_item: cell->children.back()->str = "\\DST"; delete $1; + delete limit; + delete limit2; }; specify_opt_triple: |