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authorZachary Snow <zach@zachjs.com>2021-03-18 13:38:25 -0400
committerZachary Snow <zachary.j.snow@gmail.com>2021-03-19 12:08:43 -0400
commit4f4e70876f06738fa7dda24e01ac296fe318264a (patch)
treeb7f08404ae9669d222248e328bba2f738910451e /frontends/verilog
parent6a0d1e117d5af004df897ea7329dfae507c797d2 (diff)
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sv: allow typenames as function return types
Diffstat (limited to 'frontends/verilog')
-rw-r--r--frontends/verilog/verilog_parser.y6
1 files changed, 6 insertions, 0 deletions
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ea8cc0765..91b7afddf 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -861,6 +861,7 @@ task_func_decl:
outreg->children.push_back($4);
outreg->is_signed = $4->is_signed;
$4->is_signed = false;
+ outreg->is_custom_type = $4->type == AST_WIRETYPE;
}
current_function_or_task->children.push_back(outreg);
current_function_or_task_port_id = 1;
@@ -871,6 +872,11 @@ task_func_decl:
};
func_return_type:
+ hierarchical_type_id {
+ $$ = new AstNode(AST_WIRETYPE);
+ $$->str = *$1;
+ delete $1;
+ } |
opt_type_vec opt_signedness_default_unsigned {
$$ = makeRange(0, 0, $2);
} |