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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-10 13:28:19 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-08-10 13:28:19 +0200 |
| commit | b76c72056b37d8f2b84948cbdc302b149577e648 (patch) | |
| tree | 885509824294c17444dec928d4f80f06a16af57c /frontends/verilog | |
| parent | 545a3417c81d454071b8d39b6ac88258ceb891a3 (diff) | |
| download | yosys-b76c72056b37d8f2b84948cbdc302b149577e648.tar.gz yosys-b76c72056b37d8f2b84948cbdc302b149577e648.tar.bz2 yosys-b76c72056b37d8f2b84948cbdc302b149577e648.zip | |
set default_nettype to wire for resetall
Diffstat (limited to 'frontends/verilog')
| -rw-r--r-- | frontends/verilog/preproc.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 9781a22d9..e33b0a2c3 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -961,6 +961,7 @@ frontend_verilog_preproc(std::istream &f, } if (tok == "`resetall") { + default_nettype_wire = true; continue; } |