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genrtlil.cc
Commit message (
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Author
Age
Files
Lines
*
verilog: impose limit on maximum expression width
Zachary Snow
2021-03-04
1
-0
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+6
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genrtlil: improve name conflict error messaging
Zachary Snow
2021-02-26
1
-12
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+37
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frontend: Make helper functions for printing locations.
Marcelina Kościelnicka
2021-02-23
1
-25
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+25
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verilog: support recursive functions using ternary expressions
Zachary Snow
2021-02-12
1
-0
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+35
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genrtlil: fix signed port connection codegen failures
Zachary Snow
2021-02-05
1
-1
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+5
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genrtlil: fix mux2rtlil generated wire signedness
Zachary Snow
2020-12-22
1
-0
/
+1
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Sign extend port connections where necessary
Zachary Snow
2020-12-18
1
-2
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+24
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static cast: support changing size and signedness
Kazuki Sakamoto
2020-06-19
1
-0
/
+24
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Merge pull request #2041 from PeterCrozier/struct
clairexen
2020-06-04
1
-0
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+2
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Merge branch 'master' into struct
Peter Crozier
2020-06-03
1
-1
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+1
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Generalise structs and add support for packed unions.
Peter Crozier
2020-05-12
1
-0
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+1
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Implement SV structs.
Peter Crozier
2020-05-08
1
-0
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+1
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Merge pull request #2006 from jersey99/signed-in-rtlil-wire
whitequark
2020-06-04
1
-0
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+1
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Preserve 'signed'-ness of a verilog wire through RTLIL
Vamsi K Vytla
2020-04-27
1
-0
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+1
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Add force_downto and force_upto wire attributes.
Marcelina Kościelnicka
2020-05-19
1
-1
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+1
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Merge pull request #2022 from Xiretza/fallthroughs
whitequark
2020-05-08
1
-3
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+4
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Add YS_FALLTHROUGH macro to mark case fall-through
Xiretza
2020-05-07
1
-3
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+4
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Merge pull request #2005 from YosysHQ/claire/fix1990
Claire Wolf
2020-05-07
1
-4
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+19
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Fix handling of signed indices in bit slices
Claire Wolf
2020-05-02
1
-3
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+8
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*
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Add AST_SELFSZ and improve handling of bit slices
Claire Wolf
2020-05-02
1
-1
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+7
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*
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs...
Claire Wolf
2020-05-02
1
-0
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+4
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
Eddie Hung
2020-05-04
1
-1
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+1
*
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frontend: Include complete source location instead of just `location.first_li...
Alberto Gonzalez
2020-05-01
1
-13
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+13
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ilang, ast: Store parameter order and default value information.
Marcelina Kościelnicka
2020-04-21
1
-1
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+4
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Add LookaheadRewriter for proper bitselwrite support
Claire Wolf
2020-04-16
1
-3
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+128
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Fix 5bba9c3, closes #1876
Claire Wolf
2020-04-14
1
-7
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+13
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kernel: big fat patch to use more ID::*, otherwise ID(*)
Eddie Hung
2020-04-02
1
-134
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+122
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kernel: use more ID::*
Eddie Hung
2020-04-02
1
-45
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+45
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Merge pull request #1718 from boqwxp/precise_locations
Claire Wolf
2020-03-03
1
-102
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+101
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Closes #1717. Add more precise Verilog source location information to AST and...
Alberto Gonzalez
2020-02-23
1
-102
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+101
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ast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung
2020-02-27
1
-9
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+22
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Merge pull request #1703 from YosysHQ/eddie/specify_improve
Eddie Hung
2020-02-21
1
-7
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+11
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verilog: fix $specify3 check
Eddie Hung
2020-02-13
1
-7
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+11
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partial rebase of PeterCrozier's enum work onto current master
Jeff Wang
2020-01-16
1
-2
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+6
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sv: Switch parser to glr, prep for typedef
David Shah
2019-10-03
1
-0
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+1
*
substr() -> compare()
Eddie Hung
2019-08-07
1
-1
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+1
*
genrtlil: emit \src attribute on CaseRule.
whitequark
2019-07-08
1
-0
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+1
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Add "read_verilog -pwires" feature, closes #1106
Clifford Wolf
2019-06-19
1
-1
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+20
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Fixes and cleanups in AST_TECALL handling
Clifford Wolf
2019-06-07
1
-1
/
+31
*
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into cliffo...
Clifford Wolf
2019-06-07
1
-0
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+1
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Initial implementation of elaboration system tasks
Udi Finkelstein
2019-05-03
1
-0
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+1
*
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Merge branch 'master' into wandwor
Stefan Biereigel
2019-05-27
1
-3
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+9
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Merge pull request #1044 from mmicko/invalid_width_range
Clifford Wolf
2019-05-27
1
-1
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+2
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Give error instead of asserting for invalid range, fixes #947
Miodrag Milanovic
2019-05-27
1
-1
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+2
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*
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Added support for unsized constants, fixes #1022
Miodrag Milanovic
2019-05-27
1
-2
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+7
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*
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move wand/wor resolution into hierarchy pass
Stefan Biereigel
2019-05-27
1
-97
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+14
*
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fix assignment of non-wires
Stefan Biereigel
2019-05-23
1
-16
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+19
*
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fix indentation across files
Stefan Biereigel
2019-05-23
1
-58
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+76
*
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implementation for assignments working
Stefan Biereigel
2019-05-23
1
-14
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+79
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/
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*
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Improve write_verilog specify support
Clifford Wolf
2019-05-04
1
-0
/
+3
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