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| author | Claire Wolf <claire@symbioticeda.com> | 2020-04-29 14:28:04 +0200 |
|---|---|---|
| committer | Claire Wolf <claire@symbioticeda.com> | 2020-05-02 11:21:01 +0200 |
| commit | 589ed2d97032829568e73a5858772e39088aeeeb (patch) | |
| tree | ff318592efab768ecb4f57e493cb8a260641c298 /frontends/ast/genrtlil.cc | |
| parent | bbbce0d1c58f8bfb0a615f1ed53fa046552b5adf (diff) | |
| download | yosys-589ed2d97032829568e73a5858772e39088aeeeb.tar.gz yosys-589ed2d97032829568e73a5858772e39088aeeeb.tar.bz2 yosys-589ed2d97032829568e73a5858772e39088aeeeb.zip | |
Add AST_SELFSZ and improve handling of bit slices
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 6a39bbc04..37cbb8a83 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -809,6 +809,11 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun sign_hint = false; break; + case AST_SELFSZ: + sub_width_hint = 0; + children.at(0)->detectSignWidthWorker(sub_width_hint, sign_hint); + break; + case AST_CONCAT: for (auto child : children) { sub_width_hint = 0; @@ -1267,7 +1272,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) // just pass thru the signal. the parent will evaluate the is_signed property and interpret the SigSpec accordingly case AST_TO_SIGNED: - case AST_TO_UNSIGNED: { + case AST_TO_UNSIGNED: + case AST_SELFSZ: { RTLIL::SigSpec sig = children[0]->genRTLIL(); if (sig.size() < width_hint) sig.extend_u0(width_hint, sign_hint); |