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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-21 09:15:17 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-02-21 09:15:17 -0800 |
| commit | 760096e8d2e9e2431bd5f97034bbd4ba01326649 (patch) | |
| tree | f19ca177b826e856b117f9812900959dc4d6f14e /frontends/ast/genrtlil.cc | |
| parent | cd044a2bb6adf7a5e00d4a6c075e9489d852d733 (diff) | |
| parent | ea4bd161b68cda30b5300b9275ebc0723896be02 (diff) | |
| download | yosys-760096e8d2e9e2431bd5f97034bbd4ba01326649.tar.gz yosys-760096e8d2e9e2431bd5f97034bbd4ba01326649.tar.bz2 yosys-760096e8d2e9e2431bd5f97034bbd4ba01326649.zip | |
Merge pull request #1703 from YosysHQ/eddie/specify_improve
Improve specify parser
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 76705c75f..3fb6b3e5c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1563,21 +1563,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - if (cell->type.in("$specify2", "$specify3")) { + if (cell->type == "$specify2") { int src_width = GetSize(cell->getPort("\\SRC")); int dst_width = GetSize(cell->getPort("\\DST")); bool full = cell->getParam("\\FULL").as_bool(); if (!full && src_width != dst_width) log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n"); - if (cell->type == "$specify3") { - int dat_width = GetSize(cell->getPort("\\DAT")); - if (dat_width != dst_width) - log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n"); - } cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam("\\DST_WIDTH", Const(dst_width)); } - if (cell->type == "$specrule") { + else if (cell->type == "$specify3") { + int dat_width = GetSize(cell->getPort("\\DAT")); + int dst_width = GetSize(cell->getPort("\\DST")); + if (dat_width != dst_width) + log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n"); + int src_width = GetSize(cell->getPort("\\SRC")); + cell->setParam("\\SRC_WIDTH", Const(src_width)); + cell->setParam("\\DST_WIDTH", Const(dst_width)); + } + else if (cell->type == "$specrule") { int src_width = GetSize(cell->getPort("\\SRC")); int dst_width = GetSize(cell->getPort("\\DST")); cell->setParam("\\SRC_WIDTH", Const(src_width)); |