diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-18 18:15:03 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-05-19 01:42:40 +0200 |
| commit | aee439360bba642dcbffe5b803aa9a994b11d183 (patch) | |
| tree | a5c15b4a6172ea3ff651f88174fff7d5269ad1c2 /frontends/ast/genrtlil.cc | |
| parent | 2d573a0ff680eb9f38358943fbf134f765ba1451 (diff) | |
| download | yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.gz yosys-aee439360bba642dcbffe5b803aa9a994b11d183.tar.bz2 yosys-aee439360bba642dcbffe5b803aa9a994b11d183.zip | |
Add force_downto and force_upto wire attributes.
Fixes #2058.
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d4e9baa5f..cdc3adc9c 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1055,7 +1055,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) if (!range_valid) log_file_error(filename, location.first_line, "Signal `%s' with non-constant width!\n", str.c_str()); - if (!(range_left >= range_right || (range_left == -1 && range_right == 0))) + if (!(range_left + 1 >= range_right)) log_file_error(filename, location.first_line, "Signal `%s' with invalid width range %d!\n", str.c_str(), range_left - range_right + 1); RTLIL::Wire *wire = current_module->addWire(str, range_left - range_right + 1); |