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| author | Vamsi K Vytla <vamsi.vytla@gmail.com> | 2020-04-27 09:44:24 -0700 |
|---|---|---|
| committer | Vamsi K Vytla <vamsi.vytla@gmail.com> | 2020-04-27 09:44:24 -0700 |
| commit | 5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c (patch) | |
| tree | 4a8694391c20cf6e6a8623f6e9fdc7c6daee3297 /frontends/ast/genrtlil.cc | |
| parent | 3eb24809a1d80f4b7015e6f8b1458e300727c244 (diff) | |
| download | yosys-5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c.tar.gz yosys-5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c.tar.bz2 yosys-5f9cd2e2f6cdea9f00cb5a042c7fe472fb54ef4c.zip | |
Preserve 'signed'-ness of a verilog wire through RTLIL
As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987, now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index d35335747..93fcfb396 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1058,6 +1058,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) wire->port_input = is_input; wire->port_output = is_output; wire->upto = range_swapped; + wire->is_signed = is_signed; for (auto &attr : attributes) { if (attr.second->type != AST_CONSTANT) |