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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-12 12:16:01 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-13 12:42:04 -0800 |
| commit | 7cfdf4ffa7698fa40aae401c2b8b159a6e37011a (patch) | |
| tree | c94c86d18749a16b405545aa95718254a350513a /frontends/ast/genrtlil.cc | |
| parent | cb7bc6a12fee1d948b7f91fd37f326dbd4f5ca47 (diff) | |
| download | yosys-7cfdf4ffa7698fa40aae401c2b8b159a6e37011a.tar.gz yosys-7cfdf4ffa7698fa40aae401c2b8b159a6e37011a.tar.bz2 yosys-7cfdf4ffa7698fa40aae401c2b8b159a6e37011a.zip | |
verilog: fix $specify3 check
Diffstat (limited to 'frontends/ast/genrtlil.cc')
| -rw-r--r-- | frontends/ast/genrtlil.cc | 18 |
1 files changed, 11 insertions, 7 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 94f5c0a04..05a5b45b8 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -1559,21 +1559,25 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) log_file_error(filename, linenum, "Attribute `%s' with non-constant value.\n", attr.first.c_str()); cell->attributes[attr.first] = attr.second->asAttrConst(); } - if (cell->type.in("$specify2", "$specify3")) { + if (cell->type == "$specify2") { int src_width = GetSize(cell->getPort("\\SRC")); int dst_width = GetSize(cell->getPort("\\DST")); bool full = cell->getParam("\\FULL").as_bool(); if (!full && src_width != dst_width) log_file_error(filename, linenum, "Parallel specify SRC width does not match DST width.\n"); - if (cell->type == "$specify3") { - int dat_width = GetSize(cell->getPort("\\DAT")); - if (dat_width != dst_width) - log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n"); - } cell->setParam("\\SRC_WIDTH", Const(src_width)); cell->setParam("\\DST_WIDTH", Const(dst_width)); } - if (cell->type == "$specrule") { + else if (cell->type == "$specify3") { + int dat_width = GetSize(cell->getPort("\\DAT")); + int dst_width = GetSize(cell->getPort("\\DST")); + if (dat_width != dst_width) + log_file_error(filename, linenum, "Specify DAT width does not match DST width.\n"); + int src_width = GetSize(cell->getPort("\\SRC")); + cell->setParam("\\SRC_WIDTH", Const(src_width)); + cell->setParam("\\DST_WIDTH", Const(dst_width)); + } + else if (cell->type == "$specrule") { int src_width = GetSize(cell->getPort("\\SRC")); int dst_width = GetSize(cell->getPort("\\DST")); cell->setParam("\\SRC_WIDTH", Const(src_width)); |