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author | Kazuki Sakamoto <sakamoto@splhack.org> | 2020-06-14 15:15:59 -0700 |
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committer | Kazuki Sakamoto <sakamoto@splhack.org> | 2020-06-19 17:39:20 -0700 |
commit | 185bbbe681d02874796e70a1ee147f4b8dca6cbb (patch) | |
tree | 31ad1e634e09fdd40776a8c44a407d2b6d416f69 /frontends/ast/genrtlil.cc | |
parent | 338ecbe02f8bb3cc4d69de1445c7f398a814b4e4 (diff) | |
download | yosys-185bbbe681d02874796e70a1ee147f4b8dca6cbb.tar.gz yosys-185bbbe681d02874796e70a1ee147f4b8dca6cbb.tar.bz2 yosys-185bbbe681d02874796e70a1ee147f4b8dca6cbb.zip |
static cast: support changing size and signedness
Support SystemVerilog Static Cast
- size
- signedness
- (type is not supposted yet)
Fix #535
Diffstat (limited to 'frontends/ast/genrtlil.cc')
-rw-r--r-- | frontends/ast/genrtlil.cc | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 9546558aa..e878d0dd2 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -814,6 +814,16 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun children.at(0)->detectSignWidthWorker(sub_width_hint, sign_hint); break; + case AST_CAST_SIZE: + while (children.at(0)->simplify(true, false, false, 1, -1, false, false)) { } + if (children.at(0)->type != AST_CONSTANT) + log_file_error(filename, location.first_line, "Static cast with non constant expression!\n"); + children.at(1)->detectSignWidthWorker(width_hint, sign_hint); + width_hint = children.at(0)->bitsAsConst().as_int(); + if (width_hint <= 0) + log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n"); + break; + case AST_CONCAT: for (auto child : children) { sub_width_hint = 0; @@ -1289,6 +1299,20 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) return sig; } + // changing the size of signal can be done directly using RTLIL::SigSpec + case AST_CAST_SIZE: { + RTLIL::SigSpec size = children[0]->genRTLIL(); + RTLIL::SigSpec sig = children[1]->genRTLIL(); + if (!size.is_fully_const()) + log_file_error(filename, location.first_line, "Static cast with non constant expression!\n"); + int width = size.as_int(); + if (width <= 0) + log_file_error(filename, location.first_line, "Static cast with zero or negative size!\n"); + sig.extend_u0(width, sign_hint); + is_signed = sign_hint; + return sig; + } + // concatenation of signals can be done directly using RTLIL::SigSpec case AST_CONCAT: { RTLIL::SigSpec sig; |