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* sv: fix size cast internal expression extensionZachary Snow2022-01-071-2/+9
* sv: fix size cast clipping expression widthZachary Snow2022-01-031-1/+2
* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-0/+5
* genrtlil: Fix displaying debug info in packagesKamil Rakoczy2021-11-101-1/+2
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-12/+11
* Generate an RTLIL representation of bind constructsRupert Swarbrick2021-08-131-2/+77
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+8
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-3/+6
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-161-0/+5
* sv: fix two struct access bugsZachary Snow2021-07-151-0/+4
* rtlil: Make Process handling more uniform with Cell and Wire.Marcelina Kościelnicka2021-07-121-3/+1
* ast: fix error condition causing assert to failXiretza2021-06-141-2/+1
* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-091-1/+1
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-2/+9
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* verilog: fix case expression sign and width handlingZachary Snow2021-05-251-10/+40
* verilog: Use proc memory writes in the frontend.Marcelina Kościelnicka2021-03-081-18/+38
* verilog: impose limit on maximum expression widthZachary Snow2021-03-041-0/+6
* genrtlil: improve name conflict error messagingZachary Snow2021-02-261-12/+37
* frontend: Make helper functions for printing locations.Marcelina Kościelnicka2021-02-231-25/+25
* verilog: support recursive functions using ternary expressionsZachary Snow2021-02-121-0/+35
* genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-051-1/+5
* genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-0/+1
* Sign extend port connections where necessaryZachary Snow2020-12-181-2/+24
* static cast: support changing size and signednessKazuki Sakamoto2020-06-191-0/+24
* Merge pull request #2041 from PeterCrozier/structclairexen2020-06-041-0/+2
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| * Merge branch 'master' into structPeter Crozier2020-06-031-1/+1
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| * | Generalise structs and add support for packed unions.Peter Crozier2020-05-121-0/+1
| * | Implement SV structs.Peter Crozier2020-05-081-0/+1
* | | Merge pull request #2006 from jersey99/signed-in-rtlil-wirewhitequark2020-06-041-0/+1
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| * | Preserve 'signed'-ness of a verilog wire through RTLILVamsi K Vytla2020-04-271-0/+1
* | | Add force_downto and force_upto wire attributes.Marcelina Kościelnicka2020-05-191-1/+1
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* | Merge pull request #2022 from Xiretza/fallthroughswhitequark2020-05-081-3/+4
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| * | Add YS_FALLTHROUGH macro to mark case fall-throughXiretza2020-05-071-3/+4
* | | Merge pull request #2005 from YosysHQ/claire/fix1990Claire Wolf2020-05-071-4/+19
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| * | Fix handling of signed indices in bit slicesClaire Wolf2020-05-021-3/+8
| * | Add AST_SELFSZ and improve handling of bit slicesClaire Wolf2020-05-021-1/+7
| * | Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offs...Claire Wolf2020-05-021-0/+4
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* | frontend: cleanup to use more ID::*, more dict<> instead of map<>Eddie Hung2020-05-041-1/+1
* | frontend: Include complete source location instead of just `location.first_li...Alberto Gonzalez2020-05-011-13/+13
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* ilang, ast: Store parameter order and default value information.Marcelina Kościelnicka2020-04-211-1/+4
* Add LookaheadRewriter for proper bitselwrite supportClaire Wolf2020-04-161-3/+128
* Fix 5bba9c3, closes #1876Claire Wolf2020-04-141-7/+13
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-134/+122
* kernel: use more ID::*Eddie Hung2020-04-021-45/+45
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-102/+101
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| * Closes #1717. Add more precise Verilog source location information to AST and...Alberto Gonzalez2020-02-231-102/+101
* | ast: fixes #1710; do not generate RTLIL for unreachable ternaryEddie Hung2020-02-271-9/+22
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* Merge pull request #1703 from YosysHQ/eddie/specify_improveEddie Hung2020-02-211-7/+11
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| * verilog: fix $specify3 checkEddie Hung2020-02-131-7/+11
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