iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
...
*	Add TODO to parse_xaiger	Eddie Hung	2019-06-14	1	-0/+1
*	Optimise some more	Eddie Hung	2019-06-13	1	-58/+53
*	Move ConstEvalAig to aigerparse.cc	Eddie Hung	2019-06-13	1	-3/+161
*	Add ConstEvalAig specialised for AIGs	Eddie Hung	2019-06-13	1	-3/+2
*	parse_xaiger to cope with inouts	Eddie Hung	2019-06-12	1	-6/+0
*	Consistency	Eddie Hung	2019-06-12	2	-2/+2
*	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-06-12	2	-859/+837
\|\
\| *	Fix spacing from spaces to tabs	Eddie Hung	2019-06-07	1	-362/+362
\| *	Fix spacing (entire file is wrong anyway, will fix later)	Eddie Hung	2019-06-07	1	-3/+3
\| *	Remove unnecessary std::getline() for ASCII	Eddie Hung	2019-06-07	1	-3/+0
\| *	Fix read_aiger -- create zero driver, fix init width, parse 'b'	Eddie Hung	2019-06-07	2	-13/+52
\| *	Rename label	Eddie Hung	2019-05-21	1	-6/+5
\| *	Try again	Eddie Hung	2019-05-21	1	-4/+10
\| *	Fix warning	Eddie Hung	2019-05-21	1	-3/+2
* \|	Move clean from aigerparse to abc9	Eddie Hung	2019-04-23	1	-2/+0
* \|	Tidy up	Eddie Hung	2019-04-22	1	-1/+1
* \|	Revert "Temporarily remove 'r' extension"	Eddie Hung	2019-04-22	1	-0/+18
* \|	Temporarily remove 'r' extension	Eddie Hung	2019-04-22	1	-18/+0
* \|	Merge remote-tracking branch 'origin/master' into xaig	Eddie Hung	2019-04-22	1	-3/+0
\|\\|
\| *	Add log_debug() framework	Clifford Wolf	2019-04-22	1	-2/+0
* \|	read_aiger to parse 'r' extension	Eddie Hung	2019-04-18	1	-0/+18
* \|	Ignore a/i/o/h XAIGER extensions	Eddie Hung	2019-04-17	1	-0/+7
* \|	Forgot backslashes	Eddie Hung	2019-04-12	1	-1/+1
* \|	Handle __dummy_o__ and __const[01]__ in read_aiger not abc	Eddie Hung	2019-04-12	1	-0/+4
* \|	Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig	Eddie Hung	2019-04-12	1	-12/+32
\|\ \
\| * \|	Fix inout handling for -map option	Eddie Hung	2019-04-12	1	-10/+30
* \| \|	Also cope with duplicated CIs	Eddie Hung	2019-04-12	1	-5/+23
* \| \|	Cope with an output having same name as an input (i.e. CO)	Eddie Hung	2019-04-12	1	-5/+23
\|/ /
* \|	parse_aiger() to rename all $lut cells after "clean"	Eddie Hung	2019-04-10	1	-24/+21
* \|	Fix spacing	Eddie Hung	2019-04-08	1	-29/+29
* \|	Merge branch 'master' into xaig	Eddie Hung	2019-04-08	1	-0/+1
\|\\|
\| *	Add author name	Eddie Hung	2019-03-19	1	-0/+1
* \|	parse_xaiger() to really pass single and multi-bit inout tests	Eddie Hung	2019-02-26	1	-10/+12
* \|	parse_xaiger() to cope with multi bit inouts	Eddie Hung	2019-02-26	1	-0/+11
* \|	parse_xaiger() to untransform $inout.out output ports	Eddie Hung	2019-02-25	1	-5/+20
* \|	read_aiger to accept empty string for clk_name, passable only if no latches	Eddie Hung	2019-02-25	1	-0/+2
* \|	read_aiger to work with symbol table	Eddie Hung	2019-02-21	1	-8/+47
* \|	Add attribution	Eddie Hung	2019-02-21	1	-1/+1
* \|	Merge branch 'read_aiger' into xaig	Eddie Hung	2019-02-21	1	-2/+7
\|\\|
\| *	Fix for using POSIX basename	Eddie Hung	2019-02-19	1	-2/+4
\| *	Missing OSX headers?	Eddie Hung	2019-02-17	1	-0/+5
\| *	read_aiger to ignore line after ands for ascii, not binary	Eddie Hung	2019-02-17	1	-2/+1
* \|	read_aiger to not do -purge for clean	Eddie Hung	2019-02-20	1	-1/+1
* \|	lut/not/and suffix to be ${lut,not,and}	Eddie Hung	2019-02-20	1	-13/+13
* \|	read_aiger to also rename 0 index lut when wideports	Eddie Hung	2019-02-20	1	-2/+14
* \|	read_aiger: new naming fixes	Eddie Hung	2019-02-20	1	-5/+5
* \|	read_aiger to name wires with internal name, less likely to clash	Eddie Hung	2019-02-20	1	-18/+15
* \|	Same for ascii AIGERs too	Eddie Hung	2019-02-19	1	-6/+13
* \|	read_aiger to cope with non-unique POs	Eddie Hung	2019-02-19	1	-6/+13
* \|	read_aiger to create sane $lut names, and rename when renaming driving wire	Eddie Hung	2019-02-19	1	-2/+11