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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:30:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-07 11:30:36 -0700 |
| commit | 6934f4bdd53cb226d0c8631eff691d9a96aebbce (patch) | |
| tree | 2155edb7f4233b76fe97f90cfbfcee971bf5b9f0 /frontends/aiger | |
| parent | d00ae1d6a8c0a1e147599ee27f6a4ea68f43267e (diff) | |
| download | yosys-6934f4bdd53cb226d0c8631eff691d9a96aebbce.tar.gz yosys-6934f4bdd53cb226d0c8631eff691d9a96aebbce.tar.bz2 yosys-6934f4bdd53cb226d0c8631eff691d9a96aebbce.zip | |
Fix spacing (entire file is wrong anyway, will fix later)
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index d0338e45d..32be4cf6c 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -81,9 +81,9 @@ end_of_header: else log_abort(); - RTLIL::Wire* n0 = module->wire("\\n0"); - if (n0) - module->connect(n0, RTLIL::S0); + RTLIL::Wire* n0 = module->wire("\\n0"); + if (n0) + module->connect(n0, RTLIL::S0); for (unsigned i = 0; i < outputs.size(); ++i) { RTLIL::Wire *wire = outputs[i]; |