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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 18:22:44 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 18:22:44 -0700 |
| commit | fecafb2207efc772fec49b357bc6e20ca6a25aca (patch) | |
| tree | 5aa19dda445b0d3773976b4ab712bf852ba06f15 /frontends/aiger | |
| parent | 9bfcd8006378dc0d81a1c902501a6efeb8406cba (diff) | |
| download | yosys-fecafb2207efc772fec49b357bc6e20ca6a25aca.tar.gz yosys-fecafb2207efc772fec49b357bc6e20ca6a25aca.tar.bz2 yosys-fecafb2207efc772fec49b357bc6e20ca6a25aca.zip | |
Forgot backslashes
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index e35a8ad62..f2d21f1db 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -477,7 +477,7 @@ next_line: RTLIL::Wire* wire = outputs[variable]; log_assert(wire); log_assert(wire->port_output); - if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) { + if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) { wire->port_output = false; continue; } |