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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 18:21:16 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-12 18:21:16 -0700 |
| commit | 9bfcd8006378dc0d81a1c902501a6efeb8406cba (patch) | |
| tree | 2176e0d2df239255b108feb20e8ae83dc6e9f983 /frontends/aiger | |
| parent | 482a60825b607880c5984b1b39e06e58c5f75ada (diff) | |
| download | yosys-9bfcd8006378dc0d81a1c902501a6efeb8406cba.tar.gz yosys-9bfcd8006378dc0d81a1c902501a6efeb8406cba.tar.bz2 yosys-9bfcd8006378dc0d81a1c902501a6efeb8406cba.zip | |
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7e91c8cac..e35a8ad62 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -477,6 +477,10 @@ next_line: RTLIL::Wire* wire = outputs[variable]; log_assert(wire); log_assert(wire->port_output); + if (escaped_s.in("__dummy_o__", "__const0__", "__const1__")) { + wire->port_output = false; + continue; + } if (index == 0) { // Cope with the fact that a CO might be identical |