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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-17 12:07:14 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-17 12:07:14 -0800 |
| commit | 9268a271fb8b22b089927d63f0b36d620e19704c (patch) | |
| tree | ffd36a339aa3574e70cd22f7d309fc9a4bc70f9e /frontends/aiger | |
| parent | 430a7548bca6046c812f713877253f8c3d81d805 (diff) | |
| download | yosys-9268a271fb8b22b089927d63f0b36d620e19704c.tar.gz yosys-9268a271fb8b22b089927d63f0b36d620e19704c.tar.bz2 yosys-9268a271fb8b22b089927d63f0b36d620e19704c.zip | |
read_aiger to ignore line after ands for ascii, not binary
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 7df28fe87..a1a0a08a0 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -235,6 +235,7 @@ void AigerReader::parse_aiger_ascii() RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3); module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire); } + std::getline(f, line); // Ignore up to start of next line } static unsigned parse_next_delta_literal(std::istream &f, unsigned ref) @@ -342,8 +343,6 @@ void AigerReader::parse_aiger_binary() and_cell->setPort("\\B", i2_wire); and_cell->setPort("\\Y", o_wire); } - std::getline(f, line); // Ignore up to start of next line - } struct AigerFrontend : public Frontend { |