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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 12:39:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 12:39:51 -0800 |
| commit | f9702a8abef5a9df94dfbfe16f2aa686c08c6b00 (patch) | |
| tree | b3b08f84ecebce6a4876ffd40a8351471294992d /frontends/aiger | |
| parent | 83b66861e9c669f643e096030d0b165ca45ab38c (diff) | |
| download | yosys-f9702a8abef5a9df94dfbfe16f2aa686c08c6b00.tar.gz yosys-f9702a8abef5a9df94dfbfe16f2aa686c08c6b00.tar.bz2 yosys-f9702a8abef5a9df94dfbfe16f2aa686c08c6b00.zip | |
read_aiger: new naming fixes
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 4611d9fc1..5c862b8f0 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -347,8 +347,8 @@ void AigerReader::parse_xaiger() module->rename(wire, stringf("\\%s", s.c_str())); - RTLIL::Cell* driver = module->cell(stringf("%s_lut", wire->name.c_str())); - module->rename(driver, stringf("%s_lut", wire->name.c_str())); + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(driver, stringf("%slut", wire->name.c_str())); std::getline(f, line); // Ignore up to start of next line ++line_count; @@ -385,7 +385,7 @@ void AigerReader::parse_xaiger() log_assert(wire); log_assert(wire->port_output); - RTLIL::Cell* driver = module->cell(stringf("%s_lut", wire->name.c_str())); + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); if (index == 0) module->rename(wire, RTLIL::escape_id(symbol)); @@ -396,7 +396,7 @@ void AigerReader::parse_xaiger() } if (driver) - module->rename(driver, stringf("%s_lut", wire->name.c_str())); + module->rename(driver, stringf("%slut", wire->name.c_str())); } else log_error("Symbol type '%s' not recognised.\n", type.c_str()); @@ -656,7 +656,7 @@ void AigerReader::parse_aiger_binary() log_debug("%d is an output\n", l1); const unsigned variable = l1 >> 1; const bool invert = l1 & 1; - RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "_b" : "")); // FIXME: is "_inv" the right suffix? + RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_inv" the right suffix? wire = module->wire(wire_name); if (!wire) wire = createWireIfNotExists(module, l1); |