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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 16:17:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-20 16:17:22 -0800 |
| commit | abc1c2672e2b2d2ff80b4ccf42027fd629c1ac8b (patch) | |
| tree | a8f20cd184f31c7f6041d41df2cf215368eeae93 /frontends/aiger | |
| parent | 01f8d50ba239e98de1e6a75aec314caeae297bc8 (diff) | |
| download | yosys-abc1c2672e2b2d2ff80b4ccf42027fd629c1ac8b.tar.gz yosys-abc1c2672e2b2d2ff80b4ccf42027fd629c1ac8b.tar.bz2 yosys-abc1c2672e2b2d2ff80b4ccf42027fd629c1ac8b.zip | |
read_aiger to also rename 0 index lut when wideports
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 5c862b8f0..426e88e53 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -162,9 +162,15 @@ void AigerReader::parse_aiger() int width = wp.second + 1; RTLIL::Wire *wire = module->wire(name); - if (wire) + if (wire) { + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + if (driver) + module->rename(driver, stringf("%slut", wire->name.c_str())); + } + // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; @@ -408,9 +414,15 @@ void AigerReader::parse_xaiger() int width = wp.second + 1; RTLIL::Wire *wire = module->wire(name); - if (wire) + if (wire) { + RTLIL::Cell* driver = module->cell(stringf("%slut", wire->name.c_str())); + module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0))); + if (driver) + module->rename(driver, stringf("%slut", wire->name.c_str())); + } + // Do not make ports with a mix of input/output into // wide ports bool port_input = false, port_output = false; |