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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:11:13 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 10:11:13 -0700 |
| commit | d005568f2ea8825fdd47ae871f5bdeeaf7e27635 (patch) | |
| tree | 417794fe6fb35dc5478fb6457d3bbffe0a0ccdc9 /frontends/aiger | |
| parent | bc22e2e3ee120aeb84323ce52031b895f9f62f54 (diff) | |
| download | yosys-d005568f2ea8825fdd47ae871f5bdeeaf7e27635.tar.gz yosys-d005568f2ea8825fdd47ae871f5bdeeaf7e27635.tar.bz2 yosys-d005568f2ea8825fdd47ae871f5bdeeaf7e27635.zip | |
Add TODO to parse_xaiger
Diffstat (limited to 'frontends/aiger')
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 9c6096655..c41772c92 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -398,6 +398,7 @@ void AigerReader::parse_xaiger() log_assert(wire); input_sig.append(wire); } + // TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size()) ce.clear(); ce.compute_deps(output_sig, input_sig.to_sigbit_pool()); RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size()); |