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* Added links to some liberty files to READMEClifford Wolf2014-06-281-0/+8
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* Added more calls to "hierarchy" to README fileClifford Wolf2014-06-151-3/+8
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* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-121-3/+13
| | | | allways_ff, always_comb, and always_latch
* Updated READMEClifford Wolf2014-04-181-18/+11
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* Added libs/minisat (copy of minisat git master)Clifford Wolf2014-03-121-15/+0
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* Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosysClifford Wolf2014-03-111-1/+1
| | | | (see https://github.com/cliffordwolf/yosys/pull/28)
* Updated todo items in README fileClifford Wolf2014-02-051-2/+2
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* Added constant size expression support of sized constantsClifford Wolf2014-02-011-0/+4
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* Added note about SystemVerilog assert statement to READMEClifford Wolf2014-02-011-0/+5
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* Tiny change in example script in READMEClifford Wolf2014-01-291-1/+1
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* Fixes and other changes in READMEClifford Wolf2013-12-081-7/+6
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* Tighter integration of ABC buildClifford Wolf2013-11-271-4/+2
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* Updated TODOsClifford Wolf2013-11-241-2/+1
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* Added "top" attribute to mark top module in hierarchyClifford Wolf2013-11-241-0/+5
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* Renamed "placeholder" to "blackbox"Clifford Wolf2013-11-221-2/+2
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* Enable {* .. *} feature per default (removes dependency to REJECT feature in ↵Clifford Wolf2013-11-221-2/+1
| | | | flex)
* Implemented indexed part selectsClifford Wolf2013-11-201-3/+0
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* Fixed name resolution of local tasks and functions in generate blockClifford Wolf2013-11-201-1/+0
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* Implemented part/bit select on memory readClifford Wolf2013-11-201-1/+0
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* Updated TODOs in README fileClifford Wolf2013-11-201-6/+26
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* Added init= attribute for fpga-style reset valuesClifford Wolf2013-11-201-0/+4
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* Removed done or obsolete TODO itemsClifford Wolf2013-11-071-8/+0
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* Added support for "keep" attributes on wiresClifford Wolf2013-11-051-3/+3
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* Added roadmap to readme fileClifford Wolf2013-11-021-0/+9
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* Added paragraph to README file to avoid mycells.lib confusionClifford Wolf2013-10-311-0/+3
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* README file typo fixClifford Wolf2013-10-311-1/+1
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* Some additions to the README fileClifford Wolf2013-10-311-0/+19
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* Added iopadmap passClifford Wolf2013-10-161-1/+6
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* Added recommended apt-get commands to READMEClifford Wolf2013-10-111-2/+20
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* Updated TODO section in READMEClifford Wolf2013-08-011-9/+1
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* Added web site link to READMEClifford Wolf2013-07-211-0/+8
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* Added ast frontend refactoring to TODOClifford Wolf2013-07-111-0/+1
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* Documentation updatesClifford Wolf2013-07-041-5/+2
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* Added "make abc" and "make install-abc"Clifford Wolf2013-06-081-0/+5
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* Fixed README for new show command behavior (svg vs. ps)Clifford Wolf2013-04-271-2/+6
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* Implemented TCL support (only via -c option at the moment)Clifford Wolf2013-03-281-2/+2
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* Implemented proper handling of stub placeholder modulesClifford Wolf2013-03-281-0/+6
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* Added nosync attribute and some async reset related fixesClifford Wolf2013-03-251-0/+6
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* Reorganized TODOsClifford Wolf2013-03-241-24/+13
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* Added mem2reg option to verilog frontendClifford Wolf2013-03-241-0/+3
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* added a TODOJohann Glaser2013-03-181-0/+2
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* added description of Makefile include files for build configurationJohann Glaser2013-03-181-6/+17
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* More TODOs in READMEClifford Wolf2013-03-181-1/+7
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* corrected typosJohann Glaser2013-03-171-16/+17
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Added help messages to ilang and verilog frontendsClifford Wolf2013-03-011-0/+3
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* Added more help messagesClifford Wolf2013-03-011-0/+2
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* Added help command to README (and some other README changes)Clifford Wolf2013-02-281-12/+14
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* Added some additional TODO itemsClifford Wolf2013-02-271-2/+6
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* Fixed typo in READMEClifford Wolf2013-02-271-1/+1
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* Added copyright statement to readme fileClifford Wolf2013-02-271-0/+21
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