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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-20 13:05:27 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-20 13:05:27 +0100 |
| commit | 92035fb38ef8e7ac6319af659f7d682a047d2f70 (patch) | |
| tree | addf8c0a087eac819af1d869af61608061fbfa34 /README | |
| parent | c4c299eb5a3d9c2b7c9932efb35669c09c1aacb4 (diff) | |
| download | yosys-92035fb38ef8e7ac6319af659f7d682a047d2f70.tar.gz yosys-92035fb38ef8e7ac6319af659f7d682a047d2f70.tar.bz2 yosys-92035fb38ef8e7ac6319af659f7d682a047d2f70.zip | |
Implemented indexed part selects
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 0 insertions, 3 deletions
@@ -291,9 +291,6 @@ Roadmap / Large-scale TODOs - VlogHammer: http://www.clifford.at/yosys/vloghammer.html - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim -- Missing Verilog-2005 features to be implemented soon: - - Indexed part selects - - Technology mapping for real-world applications - Add "mini synth script" feature to techmap pass - Add const-folding via cell parameters to techmap pass |