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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 00:36:19 +0100 |
| commit | 7fccad92f76ddeee653d5dfec17868e9766a683a (patch) | |
| tree | c85e80d5652780f3b543e5937f6e7c6a1d191778 /README | |
| parent | cd71c70b4f55c89cdcfd6da23ff5f2002cb7d49d (diff) | |
| download | yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.gz yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.tar.bz2 yosys-7fccad92f76ddeee653d5dfec17868e9766a683a.zip | |
Added more help messages
Diffstat (limited to 'README')
| -rw-r--r-- | README | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -213,6 +213,8 @@ TODOs / Open Bugs - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees +- Add commands 'delete' (remove objects) and 'attr' (get, set and remove attributes) + - TCL and Python interfaces to frontends, passes, backends and RTLIL - Additional internal cell types: $pla and $lut |