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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-20 10:51:32 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-20 10:51:32 +0100 |
| commit | 19dba2561ece488543e1728ba800386943abb77c (patch) | |
| tree | 1388ba1895b2caba3f832ac0646c1224cfe1e619 /README | |
| parent | d248419fe0ec1f35d2f18b4f4aaf2c9525588fac (diff) | |
| download | yosys-19dba2561ece488543e1728ba800386943abb77c.tar.gz yosys-19dba2561ece488543e1728ba800386943abb77c.tar.bz2 yosys-19dba2561ece488543e1728ba800386943abb77c.zip | |
Implemented part/bit select on memory read
Diffstat (limited to 'README')
| -rw-r--r-- | README | 1 |
1 files changed, 0 insertions, 1 deletions
@@ -293,7 +293,6 @@ Roadmap / Large-scale TODOs - Missing Verilog-2005 features to be implemented soon: - Fix corner cases with contextual name lookup - - Part select on memory read - Indexed part selects - Technology mapping for real-world applications |