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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:58:05 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 17:58:05 +0100 |
| commit | 620b7c900a851526339c265ba6ea9510530de985 (patch) | |
| tree | b5b68fc26202a0885ff83cfb19289f200be1c362 /README | |
| parent | ae798d3fd5dc6bdd82083cce3994f449b829995e (diff) | |
| download | yosys-620b7c900a851526339c265ba6ea9510530de985.tar.gz yosys-620b7c900a851526339c265ba6ea9510530de985.tar.bz2 yosys-620b7c900a851526339c265ba6ea9510530de985.zip | |
Updated TODOs
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 1 insertions, 2 deletions
@@ -296,8 +296,7 @@ Roadmap / Large-scale TODOs - yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim - Technology mapping for real-world applications - - Add "mini synth script" feature to techmap pass - - Add const-folding via cell parameters to techmap pass + - Add bit-wise const-folding via cell parameters to techmap pass - Rewrite current stdcells.v techmap rules (modular and clean) - Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.) |