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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-01 08:03:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-01 08:03:00 +0100 |
| commit | 8a6b0a35207578342c10113b29ca3a303092c37a (patch) | |
| tree | b738c06723592a1aba84e19adef4302b0d1a44f0 /README | |
| parent | 51c2b797b34e1681bc5dbfcbebc1f45ca2294c0b (diff) | |
| download | yosys-8a6b0a35207578342c10113b29ca3a303092c37a.tar.gz yosys-8a6b0a35207578342c10113b29ca3a303092c37a.tar.bz2 yosys-8a6b0a35207578342c10113b29ca3a303092c37a.zip | |
Added help messages to ilang and verilog frontends
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -170,6 +170,9 @@ Verilog Attributes and non-standard features - The 'full_case' attribute on case statements is supported (also the non-standard "// synopsys full_case" directive) +- The 'parallel_case' attribute on case statements is supported + (also the non-standard "// synopsys parallel_case" directive) + - The "// synopsys translate_off" and "// synopsys translate_on" directives are also supported (but the use of `ifdef .. `endif is strongly recommended instead). |