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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-28 12:26:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-28 12:26:17 +0100 |
| commit | 73fba5164ffce53c766cc82dc0825f23baf996d3 (patch) | |
| tree | d437845c3ff88ecbc1a13c18fc6bbbe501678c01 /README | |
| parent | b9870a364e35d8159a8bcc8c535a2aa971e78af9 (diff) | |
| download | yosys-73fba5164ffce53c766cc82dc0825f23baf996d3.tar.gz yosys-73fba5164ffce53c766cc82dc0825f23baf996d3.tar.bz2 yosys-73fba5164ffce53c766cc82dc0825f23baf996d3.zip | |
Implemented TCL support (only via -c option at the moment)
Diffstat (limited to 'README')
| -rw-r--r-- | README | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -246,8 +246,8 @@ TODOs / Open Bugs - Actually use range information on parameters - Add brief source code documentation to most passes and kernel code - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees - - Add commands 'delete' (remove objects) and 'attr' (get, set and remove attributes) - - TCL and Python interfaces to frontends, passes, backends and RTLIL + - Add 'edit' command for changing the design (delete, add, modify objects) + - Improve TCL support and add 'list' command for inspecting the design from TCL - Additional internal cell types: $pla and $lut - Support for registering designs (as collection of modules) to CellTypes - Smarter resource sharing pass (add MUXes and get rid of duplicated cells) |