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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-24 05:03:43 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-24 05:03:43 +0100 |
| commit | 28093d9dd288484daa9df17585c1c9f174498359 (patch) | |
| tree | 3940c6d3bd95f7c983c76cd6e54bd04216867f3d /README | |
| parent | a4edecb0cae0524b6f42d1a2c64af5a940c67a2f (diff) | |
| download | yosys-28093d9dd288484daa9df17585c1c9f174498359.tar.gz yosys-28093d9dd288484daa9df17585c1c9f174498359.tar.bz2 yosys-28093d9dd288484daa9df17585c1c9f174498359.zip | |
Added "top" attribute to mark top module in hierarchy
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -262,6 +262,11 @@ Verilog Attributes and non-standard features initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis to add the necessary reset logic. +- The "top" attribute on a module marks this module as the top of the + design hierarchy. The "hierarchy" command sets this attribute when called + with "-top". Other commands, such as "flatten" and various backends + use this attribute to determine the top module. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset |