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* Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-2726-246/+537
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| * abc9_ops: add commentsEddie Hung2020-01-271-1/+13
| * read_aiger: set abc9_box_seq attrEddie Hung2020-01-241-0/+1
| * abc9: -reintegrate recover type from existing cell, check against boxidEddie Hung2020-01-231-30/+19
| * simple_abc9 tests to discard whitebox before write for simEddie Hung2020-01-232-2/+3
| * abc9: warning message if no modules selectedEddie Hung2020-01-231-0/+6
| * Test for (* keep *)-ed abc9_box_idEddie Hung2020-01-231-0/+16
| * abc9_ops: -prep_xaiger to skip (* keep *) cellsEddie Hung2020-01-231-0/+2
| * abc_box_id -> abc9_box_id in testEddie Hung2020-01-231-1/+1
| * abc9_ops -prep_dff: insert async s/r mux in holes when replacing $_DFF_*Eddie Hung2020-01-231-31/+37
| * alumacc: undo accidental commitEddie Hung2020-01-221-14/+5
| * Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-221-1/+1
| * read_aiger: also parse abc9_mergeabilityEddie Hung2020-01-222-2/+6
| * Merge remote-tracking branch 'origin/eddie/abc9_fixes' into eddie/abc9_refactorEddie Hung2020-01-222-4/+6
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| | * abc9: error out if flip-flop init is 1'b1 for '-dff'Eddie Hung2020-01-221-0/+2
| | * abc9: fix scratchpad entry abc9.verifyEddie Hung2020-01-221-4/+4
| * | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-2116-156/+365
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| | * Merge pull request #1637 from YosysHQ/mwk/fix-1634Claire Wolf2020-01-211-9/+17
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| | | * fsm_detect: Add a cache to avoid excessive CPU usage for big mux networks.Marcin Kościelnicki2020-01-141-9/+17
| | * | Merge pull request #1629 from YosysHQ/mwk/edif-zClaire Wolf2020-01-211-0/+2
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| | | * | edif: Just ignore connections to 'zMarcin Kościelnicki2020-01-131-0/+2
| | * | | Merge pull request #1621 from YosysHQ/clifford/fminitClaire Wolf2020-01-202-0/+198
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| | | * | | Add fminit passClifford Wolf2020-01-092-0/+198
| | * | | | Merge pull request #1643 from YosysHQ/eddie/cleanup_arith_mapEddie Hung2020-01-182-125/+88
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| | | * | | | Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623Eddie Hung2020-01-172-119/+82
| | | * | | | +/xilinx/arith_map.v fix $lcu ruleEddie Hung2020-01-171-6/+6
| | * | | | | Merge pull request #1602 from niklasnisbeth/ice40-init-vals-warningDavid Shah2020-01-181-2/+8
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| | | * | | | | ice40: Demote conflicting FF init values to a warningNiklas Nisbeth2019-12-311-2/+8
| | * | | | | | Merge pull request #1645 from YosysHQ/eddie/fix1644Eddie Hung2020-01-179-20/+52
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| | | * | | | | xilinx_dsp: another typo; move xilinx specific testEddie Hung2020-01-172-1/+1
| | | * | | | | ice40_dsp: fix typoEddie Hung2020-01-172-2/+13
| | | * | | | | ConsistencyEddie Hung2020-01-172-4/+6
| | | * | | | | xilinx_dsp: add parameter defaultsEddie Hung2020-01-171-7/+7
| | | * | | | | Add #1644 testcaseEddie Hung2020-01-172-0/+2
| | | * | | | | synth_ice40: call wreduce before mul2dspEddie Hung2020-01-171-1/+2
| | | * | | | | ice40_dsp: add testEddie Hung2020-01-171-0/+11
| | | * | | | | ice40_dsp: add default values for parametersEddie Hung2020-01-172-11/+11
| | | * | | | | ice40_dsp: tolerant of fanout-less outputs, as well as all-zero inputsEddie Hung2020-01-171-0/+5
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| * | | | | | read_aiger: discard LUT inputs with nodeID == 0; not < 2Eddie Hung2020-01-211-1/+1
| * | | | | | read_aiger: ignore constant inputs on LUTsEddie Hung2020-01-211-3/+7
| * | | | | | write_xaiger: fix for (* keep *) on flop outputEddie Hung2020-01-212-3/+18
| * | | | | | abc9: add some log_{push,pop}() as per @nakengelhardtEddie Hung2020-01-172-5/+19
* | | | | | | Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_req...Eddie Hung2020-01-153-3/+16
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| * | | | | | Merge remote-tracking branch 'origin/master' into eddie/abc9_refactorEddie Hung2020-01-153-3/+16
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| | * | | | | Merge pull request #1639 from YosysHQ/eddie/fix_read_xaigerEddie Hung2020-01-152-2/+14
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| | | * | | | | abc9: aAdd test to check $_NOT_s are absorbedEddie Hung2020-01-151-0/+12
| | | * | | | | read_aiger: $lut prefix in frontEddie Hung2020-01-151-2/+2
| | * | | | | | Merge pull request #1636 from YosysHQ/eddie/fix_synth_xilinx_WMiodrag Milanović2020-01-151-1/+1
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| | | * | | | | synth_xilinx: fix default W value for non-xc7Eddie Hung2020-01-141-1/+1
* | | | | | | | Update README.md for (* abc9_required *)Eddie Hung2020-01-151-4/+9
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