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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-15 16:42:27 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-15 16:42:27 -0800 |
| commit | b0605128b633f64b07107ba3a673f406e96d42ad (patch) | |
| tree | f7c106275389488b5400bace823bc4cd5c8c4001 | |
| parent | 168c9d5871e331341058b026cf9b4f6a99a0f759 (diff) | |
| parent | 03ce2c72bb4e8cd32df994dec04815fa5ecec6fe (diff) | |
| download | yosys-b0605128b633f64b07107ba3a673f406e96d42ad.tar.gz yosys-b0605128b633f64b07107ba3a673f406e96d42ad.tar.bz2 yosys-b0605128b633f64b07107ba3a673f406e96d42ad.zip | |
Merge remote-tracking branch 'origin/eddie/abc9_refactor' into eddie/abc9_required
| -rw-r--r-- | frontends/aiger/aigerparse.cc | 4 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 | ||||
| -rw-r--r-- | tests/techmap/abc9.ys | 13 |
3 files changed, 16 insertions, 3 deletions
diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index cf9b33b3c..b5c861936 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -922,9 +922,9 @@ void AigerReader::post_process() if (cell->type != "$lut") continue; auto y_port = cell->getPort("\\Y").as_bit(); if (y_port.wire->width == 1) - module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str())); + module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str())); else - module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset)); + module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset)); } } diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 77be8299c..3dc05cd10 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -562,7 +562,7 @@ struct SynthXilinxPass : public ScriptPass if (active_design->scratchpad.count(k)) abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k).c_str()); else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k).c_str()); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k, RTLIL::constpad.at("synth_xilinx.abc9.xc7.W")).c_str()); if (nowidelut) abc9_opts += " -lut +/xilinx/abc9_xc7_nowide.lut"; else diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index d5a63e1cb..2140dde26 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -52,6 +52,7 @@ equiv_opt -assert abc9 -lut 4 design -load postopt select -assert-count 2 t:$lut + design -reset read_verilog -icells <<EOT module top(input a, b, output o); @@ -66,3 +67,15 @@ equiv_opt -assert abc9 -lut 4 design -load postopt select -assert-count 1 t:$lut select -assert-count 1 t:$_AND_ + + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +assign o = ~(a & b); +endmodule +EOT +abc9 -lut 4 +clean +select -assert-count 1 t:$lut +select -assert-none t:$lut t:* %D |