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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 15:41:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 15:41:55 -0800 |
| commit | 78ffd5d193a72a024204cae09ff4ab05238ed311 (patch) | |
| tree | 323c45ded2b4106dae4655ffc6f18e246bc7841c | |
| parent | ad6c49fff12e27d99c1fc15850857e5129dd76ee (diff) | |
| download | yosys-78ffd5d193a72a024204cae09ff4ab05238ed311.tar.gz yosys-78ffd5d193a72a024204cae09ff4ab05238ed311.tar.bz2 yosys-78ffd5d193a72a024204cae09ff4ab05238ed311.zip | |
synth_ice40: call wreduce before mul2dsp
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 121bcff1f..d92e40726 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,8 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("memory_dff"); + run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first + run("wreduce t:$mul"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); |